module div_5 (clk_in, clk_out, reset);input clk_in, reset;output clk_out; reg[2:0] gare; reg clk_out;initialbegingare = 4; clk_out = 0;endalways (clk_in)begin if(!reset) clk_out = 0;elseif (gare == 0) beginclk_out = ~clk_out;gare = 4;endelse gare =