module DDS(clk,rst_n,en,fword,pword,da_data); input clk; input rst_n; input en; input [31:0]fword; input [11:0]pword; output [11:0]da_data; reg[31:0]f_cnt; reg[31:0]r_fword; reg[11:0]r_pword; wire[11:0]rom_addr; always(posedge clk or negedge rs