Razavi_Monolithic_Phase-Locked_Loops_and_Clock_Rec

Abstract—An enhancement to a conventional integer- phaselocked loop (PLL) is introduced, analyzed, and demonstrated experimentally to significantly reduce voltage-controlled oscillator (VCO) phase noise. The enhancement, which involves periodically

A 320 GHz fully integrated terahertz imaging system is reported. The system is composed of a phaselocked high-power transmitter and a coherent high-sensitivity subharmonic-mixing receiver, which are fabricated using a 130 nm SiGe BiCMOS technology (

摘　要：针对直接数字频率合成（DDS）和集成锁相环（PLL）技术的特 性，提出了一种新的DDS激励PLL系统频率合成时钟发生器方案。分析了频率合成系统相位噪 声和杂散抑制的方法，介绍了主要器件AD9854和ADF4106的性能。  　　关键词：直接数字频率合成；锁相环；相位噪声；杂散抑制 　　1　引言 　　高性能合成频率广泛应用在现代通信、雷达和电子测量等技术领域中。频率合成方法主要有 3种： 　　(1)直接合成法，他利用混频器、倍频器、分频器和带通滤波器完成对频率的算术运算。 　　(2)应用锁