The SDRAM controller is designed for the Virtex V300bg432-6. It's simulated with Micron SDRAM models. The design is verified with backannotated simulation at 125MHz
This application note describes a data capture technique for a high-performance DDR2 SDRAM interface. This technique uses the Input Serializer/Deserializer (ISERDES) and Output Serializer/Deserializer (OSERDES) features available in every Virtex®-4
