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  1. A 960-Mb/s/pin Interface for Skew-Tolerant Bus Using Low Jitter PLL

  2. This paper describes an I/O scheme for use in a highspeed bus which eliminates setup and hold time requirements between clock and data by using an oversampling method. The I/O circuit uses a low jitter phase-locked loop (PLL) which suppresses the ef
  3. 所属分类:其它

    • 发布日期:2010-12-08
    • 文件大小:229376
    • 提供者:dongfangtime
  1. Clocking in Modern VLSI Systems

  2. 1 Introduction and Overview Thucydides Xanthopoulos . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1 The Clock Design Problem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
  3. 所属分类:硬件开发

    • 发布日期:2012-03-31
    • 文件大小:12582912
    • 提供者:kermitshen
  1. Skew-Tolerant_Domino_Circuits.pdf )

  2. Abstract—Domino circuits are widely used in high-performance CMOS microprocessors. However, textbook domino pipelines suffer significant timing overhead from clock skew, latch delay, and the inability to borrow time. To eliminate this overhead, some
  3. 所属分类:电子商务

    • 发布日期:2013-04-17
    • 文件大小:211968
    • 提供者:didiqlx