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  1. Practical Statecharts in C C++ Quantum Programming for Embedded Systems

  2. Chapter 1: Whirlwind Tour of Quantum Programming Chapter 2: A Crash Course in Statecharts Chapter 3: Standard State Machine Implementations Chapter 4: Implementing Behavioral Inheritance Chapter 5: State Patterns Chapter 6: Inheriting State Models S
  3. 所属分类:C

    • 发布日期:2009-12-18
    • 文件大小:2mb
    • 提供者:ewan1983
  1. 信号与系统 奥本海默 习题答案

  2. 信号与系统 奥本海默 习题答案 英文 Exercise Ch. 1 1.1 Express each of the following complex numbers in Cartesian form (x+jy): (3) ejp/2 = cos(p/2)+j sin(p/2)=j (6)ejp/4 =[cos(p/4)+j sin(p/4)]=1+j 1.2 Express each of the following complex numbers in polar form (r ej
  3. 所属分类:C

    • 发布日期:2010-09-18
    • 文件大小:406kb
    • 提供者:shushengrufeng
  1. Hdl Chip Design

  2. A practival guide for designning, synthesizing and simulating ASICs and FPGAs using VHDL or Verilog. PDF 文档
  3. 所属分类:硬件开发

    • 发布日期:2011-09-09
    • 文件大小:38mb
    • 提供者:shan123456
  1. Designing-Synthesizing- and Simulating ASICs and FPGAs using VHDL or Verilog

  2. A Practical Guide for Designing, Synthesizing, and Simulating ASICs and FPGAs using VHDL or Verilog 最为经典的讲述VHDL以及Verilog 设计的宝典书籍!设计范例涵盖很多设计中经常用的设计模块,堪称IC设计的 “词典”, 书中的很多范例都可以作为你设计应用中的IP进行应用!!
  3. 所属分类:其它

    • 发布日期:2011-10-03
    • 文件大小:38mb
    • 提供者:c00lb0ycw
  1. Reasoning with Bayesian Networks 2009

  2. This book provides a thorough introduction to the formal foundations and practical applications of Bayesian networks. It provides an extensive discussion of techniques for building Bayesian networks that model real-world situations, including techni
  3. 所属分类:其它

    • 发布日期:2012-03-21
    • 文件大小:10mb
    • 提供者:lmshspring
  1. virtual woodcuts from images

  2. We present in this paper a technique for synthesizing virtual woodcutsbased on real images. Woodcuts are aancient form of art in which an image is printed from a block of carved wood. Our solution is fully automatic, but it also allows a great deal
  3. 所属分类:其它

    • 发布日期:2012-09-24
    • 文件大小:3mb
    • 提供者:aynstan
  1. Modeling and Reasoning with Bayesian Networks

  2. This book provides a thorough introduction to the formal foundations and practical applications of Bayesian networks. It provides an extensive discussion of techniques for building Bayesian networks that model real-world situations, including techni
  3. 所属分类:网络基础

    • 发布日期:2013-06-02
    • 文件大小:10mb
    • 提供者:mainframecce
  1. Fuzzy Control Systems

  2. Foreword Author's Biographical Information Part A—General Theory Chapter 1—Learning Algorithms for Neuro-Fuzzy Networks 1 Introduction 2 Neuro-Fuzzy Networks 2.1 The Conventional Fuzzy Model 2.2 From Fuzzy to Neuro-Fuzzy 2.3 Initialization 2.4 Train
  3. 所属分类:C

    • 发布日期:2008-10-06
    • 文件大小:17mb
    • 提供者:giliwala
  1. Introducation to Meta Analysis

  2. This book provides a clear and thorough introduction to meta-analysis, the process of synthesizing data from a series of separate studies. Meta-analysis has become a critically important tool in fields as diverse as medicine, pharmacology, epidemiol
  3. 所属分类:专业指导

    • 发布日期:2014-05-11
    • 文件大小:6mb
    • 提供者:mengruyan2014
  1. Holo-graphics A Framework for Synthesizing Hologram

  2. Holo-graphics A Framework for Synthesizing Hologram of Complex Object Scene 讲全息的
  3. 所属分类:专业指导

    • 发布日期:2014-09-15
    • 文件大小:640kb
    • 提供者:manbuyunduan89
  1. A Practical Guide for Designing, Synthesizing, and Simulating ASICs

  2. A Practical Guide for Designing, Synthesizing, and Simulating ASICs and FPGAs using VHDL or Verilog.pdf
  3. 所属分类:硬件开发

    • 发布日期:2014-09-29
    • 文件大小:38mb
    • 提供者:mekel
  1. A Practical Guide for Designing, Synthesizing, and Simulating ASICs and FPGAs

  2. A Practical Guide for Designing, Synthesizing, and Simulating ASICs and FPGAs using VHDL or Verilog FPGA和ASIC开发非常有用的一本书,书中以实例讲解了许多开发思想和开发技巧,对提高逻辑设计的工作频率及效率有非常好的指导意义
  3. 所属分类:硬件开发

    • 发布日期:2015-05-14
    • 文件大小:38mb
    • 提供者:u012557434
  1. abbr_ Synthesizing, and Simulating ASICs and FPGAs using VHDL or Verilog.part01

  2. abbr_ Synthesizing, and Simulating ASICs and FPGAs using VHDL or Verilog.part01
  3. 所属分类:硬件开发

    • 发布日期:2008-11-26
    • 文件大小:3mb
    • 提供者:lulu5674
  1. abbr_ Synthesizing, and Simulating ASICs and FPGAs using VHDL or Verilog.part02

  2. abbr_ Synthesizing, and Simulating ASICs and FPGAs using VHDL or Verilog.part02
  3. 所属分类:硬件开发

    • 发布日期:2008-11-26
    • 文件大小:3mb
    • 提供者:lulu5674
  1. abbr_ Synthesizing, and Simulating ASICs and FPGAs using VHDL or Verilog.part04

  2. abbr_ Synthesizing, and Simulating ASICs and FPGAs using VHDL or Verilog.part04
  3. 所属分类:硬件开发

    • 发布日期:2008-11-26
    • 文件大小:3mb
    • 提供者:lulu5674
  1. abbr_ Synthesizing, and Simulating ASICs and FPGAs using VHDL or Verilog.part03

  2. abbr_ Synthesizing, and Simulating ASICs and FPGAs using VHDL or Verilog.part03
  3. 所属分类:硬件开发

    • 发布日期:2008-11-26
    • 文件大小:3mb
    • 提供者:lulu5674
  1. abbr_ Synthesizing, and Simulating ASICs and FPGAs using VHDL or Verilog.part05

  2. abbr_ Synthesizing, and Simulating ASICs and FPGAs using VHDL or Verilog.part05
  3. 所属分类:硬件开发

    • 发布日期:2008-11-26
    • 文件大小:3mb
    • 提供者:lulu5674
  1. abbr_ Synthesizing, and Simulating ASICs and FPGAs using VHDL or Verilog.part06

  2. abbr_ Synthesizing, and Simulating ASICs and FPGAs using VHDL or Verilog.part06
  3. 所属分类:硬件开发

    • 发布日期:2008-11-26
    • 文件大小:3mb
    • 提供者:lulu5674
  1. A.Practical.Guide.for.Designing.Synthesizing.and.Simulating.ASICs.and.FPGAs

  2. A.Practical.Guide.for.Designing.Synthesizing.and.Simulating.ASICs.and.FPGAs.using.VHDL.or.Verilog
  3. 所属分类:讲义

    • 发布日期:2018-07-20
    • 文件大小:46mb
    • 提供者:spicalai
  1. Multi-Valued Neural Network Trained by Differential Evolution for Synthesizing Multiple-Valued Functions

  2. Multi-Valued Neural Network Trained by Differential Evolution for Synthesizing Multiple-Valued Functions
  3. 所属分类:其它

    • 发布日期:2021-02-10
    • 文件大小:159kb
    • 提供者:weixin_38592256
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