LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY Vhdl1 IS PORT ( a : IN bit_vector(2 downto 0); s : OUT bit_vector(1 downto 0) ); END Vhdl1; ARCHITECTURE bd OF Vhdl1 IS
LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY selecter IS PORT ( a : IN bit_vector(2 downto 0); f : OUT bit ); END selecter; ARCHITECTURE bd OF selecter IS
