文件名称:
A Verilog HDL Test Bench Primer
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文件大小: 64kb
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上传时间: 2010-07-20
详细说明： This applications note and the included Verilog source code describe how to apply stimulus to a behavioral or gate level description of a CPLD design. The designer should have access to a Verilog simulator and be familiar with its’ basic functionality. In short, the Verilog code for each of the individual modules is compiled and the simulation is run. By applying stimulus and simulating the design, the designer can be sure the correct functionality of the design is achieved. This design uses a loadable 4-bit counter and test ben ch to illustrate the basic elements of a Verilog simulation. The design is instantiated in a test bench, stimulus is applied to the inputs, and the outputs are monitored for the desired results. ...展开收缩
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