说明: --27MHZ分频成1hz: LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY FENPIN IS PORT(CLK_IN:IN STD_LOGIC; CLK_OUT:OUT STD_LOGIC); END ENTITY FENPIN; ARCHITECTURE BEHAVE OF FENPIN IS CONSTANT BB:INTEGER:=12;--------------- <shaoqso111> 上传 | 大小:1mb