说明: VHDL语言写的十进制频率计数器 ============================== library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity cnt10 is port (rst,clk,ena:in std_logic; cout: out std_logic; outy :out std_logic_vector(3 downto 0)); end cnt10; arch
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