说明: 一位二进制全减器设计 源代码 ARCHITECTURE dataflow OF full_adder IS signal op:std_logic; BEGIN process begin op<=not y;end if; s <= x XOR op AFTER tpd; sum <= s XOR c_in AFTER tpd; c_out <= (x AND op) OR( s AND c_in) AFTER 2* tpd; END dataflow; 5 <cai758328543> 上传 | 大小:336kb