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[硬件开发] NT5CB64M16GP-EK.pdf
说明: 南亚DDR3资料 NT5CB64M16GP-EK JEDEC DDR3 Compliant - 8n Prefetch Architecture - Differential Clock(CK/) and Data Strobe(DQS/) - Double-data rate on DQs, DQS and DM Data Integrity - Auto Self Refresh (ASR) by DRAM built-in TS - Auto Refresh and S<ylm1981> 上传 | 大小:6mb