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文件名称: Intel(R) 64 Architecture x2APIC Specification
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  文件大小: 324kb
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  上传时间: 2009-06-14
  提 供 者: sqc_****
 详细说明: The xAPIC architecture provided a key mechanism for interrupt delivery in many generations of Intel processors and platforms across different market segments. This document describes the x2APIC architecture which is extended from the xAPIC archi- tecture (the latter was first implemented on Intel(R) Pentium(R) 4 Processors, and extended the APIC architecture implemented on Pentium and P6 processors). Exten- sions to the xAPIC architecture are intended primarily to increase processor addres- sability. The x2APIC architecture provides backward compatibility to the xAPIC architecture and forward extendability for future Intel platform innovations. Specifi- cally, x2APIC * Retains all key elements of compatibility to the xAPIC architecture: — delivery modes, — interrupt and processor priorities, — interrupt sources, — interrupt destination types; * Provides extensions to scale processor addressability for both the logical and physical destination modes; * Adds new features to enhance performance of interrupt delivery; * Reduces complexity of logical destination mode interrupt delivery on link based architectures. ...展开收缩
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