SPIS_Programming_Guide_V1.0.pdf核心板资料，详细地描述了一款名字叫做M

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详细说明：核心板资料，详细地描述了一款名字叫做MT7688的核心板的使用方法等待，就是MT76788的datasheetMediaTek mt7688 SPI Slave MEDIATEK Labs② Programming guide Table of contents 1. SPIS 1.1.O 1 1.2, Protocol 13. Programming sequence,…… 1.4. Protocol Timing……… 1.5. Interrupt 8 1.6. Operation Register.. 8 1.7. Register Descriptions :·:··· ::::::.. c 2015-2017 Media tek inc Page ii of ii his document contains information that is proprietary to Media tek inc. ( "Media Tek")and/ or its licensor(s) Any unauthorized use, reproduction or disclosure of this document in whole or in part is strictly prohibited MEDIATEK Labs( MediaTek mt7688 SPI Slave Programming Guide Lists of Tables and figures c 2015-2017 Media tek inc Page iii of ii his document contains information that is proprietary to Media tek inc. ( "Media Tek")and/ or its licensor(s) Any unauthorized use, reproduction or disclosure of this document in whole or in part is strictly prohibited MediaTek mt7688 SPI Slave MEDIATEK Labs( Programming guide 1。sP|S The SPl slave module translates the 16bits SPI serial protocol to create either rbus or Pbus master transaction, for accessing dRAm data or configuring registers 1.1. Overview There is no software required to run on mediatek Mt7688 SPl slave the only requirement is to setup pin -control for SPl slave, which means to disable Ethernet ports 1 to 4 (to set in loT mode) For SPl master to connect to MT7688 SPl slave, there is a protocol to follow(see section 1.2, "Protocol), registers REGO to REG4 in section 1.6.1, "Register of SPl Slave Interface"are used to get dram(rbus data from or configuring registers(Pbus)on MT7688 c 2015-2017 Media tek inc Page 1 of 12 his document contains information that is proprietary to Media tek Inc. ("Media tek")and/ or its licensor(s) Any unauthorized use, reproduction or disclosure of this document in whole or in part is strictly prohibited MEDIATEK Labs(② MediaTek mt7688 SPI Slave Programming guide 1.2 Protoco KF1 ahb wd (reg017:0]) reg addr 7h04 AHB write data[7: 0] SPI MOSI ahb wd W SPI MOSI (reg01[15:8]) 工工 reg_ addr 7h05 5 AHB write data[15: 8 ahb wd (reg01[23:6]) reg addr 7h06 AHB write data[ 23: 16 ahb wd reg addr 7h07 AHB write data[31: 24] SPI MOS (reg0131:24]) ahb addr (rego2[7:0] reg addr 7h08 AHB bus address[7: 0 SPI MOSI reg addr 7' h09 AHB bus address[ 15: 8 SPI MOSI (reg02[15:8】) ahb addr (reg02[23:16]) reg addr 7hOA AHB bus address[23: 16 SPI MOSI (reg02[31: 241)w reg addr /h0B AHB bus address[31: 24] SPI MOSI 2 b00: reserved 2 b01: reserved 2b10: word(4bytes) 2b11: reserved ahb CMD (reg03[7:0]) escm=p也1m0!] ert by Rbus d 1b1: Assert by 1b1: write ahb ack R SPI MOSI (rego4[7:0]) reg addr 7h10 8"h0 8hxx 8 bits ack =(7ho, intf_busy] SPI MISO 1'b0: AHB intt b1: AHB inff executing cmd SPI MOSI (rego Ir O R reg addr /h00 8h0 8h AHB read data[7: 0 SPI MISO ahb rd 8"h0 SPI MOSI (reg00[15:8 reg addr 7h01 AHB read data[15: 8 SPI MISO ahb rd R (reg00[23:16】]) reg addr 7h02 8h0 8 hxx AHB read data[23: 16 SPI MISO ahb rd R (reg0031:24]) reg addr 7h03 8"h0 8 hxx AHB read data[31: 24] There are 5 registers in this module rego is the read data from ahB. Rego1 is the write data that programmers want to write to AHB. Reg02 is the address that programmers want to write/ read to/from AHB. the configured value must be a physical address. Rego3 is the command that applies to aHb protocol. Reg04 is the status for polling to make sure ahb bus is idle or busy. C 2015-2017 Mediatek Page 2 of 12 his document contains information that is proprietary to Media tek Inc. ("Media tek")and/ or its licensor(s) Any unauthorized use, reproduction or disclosure of this document in whole or in part is strictly prohibited MEDIATEK Labs( MediaTek mt7688 SPI Slave Programming Guide Before programming AHB/APB registers, programmers should check reg04 bito to see if ahb is idle. Programmers can set reg03 (cmd register) to kick SPIS2AHB module to write/read one byte/halfword/word/dword to/from AHB/APB Before SPI write/read to/ from AHB, programmers should guarantee ahb bus is non-busy by checking spitoahb spi rego[0] to see if it equals to 1 b0 1.3. Programming Sequence 1.3.1 Standard mode 1 Example 1: Write 0x0123 4567 data to the register at address 0x1013 0004 Stepl Check if SPIS is idle. SPI master asserts following data on SPl_ MOSI 1′b0,7′210,8′hxx}// Read SPIs status reg0 Wait until the SPl_MiSo returned data bit[o]=0, which indicates the rbus/pbus interface of Spis is idle and ready to execute a new access command Ste Prepare commands for bus accessing SPl master asserts following data on SPl MOSi respectively 1 b1, 7 004,8h67// put bus write data [7: 0] into SPIs reg01[7: 0] 1′b1,705,8′h45}//putb ite data [15:8] into SPIs rego1[15: 81 11 b1, 7006, h231// put bus write data [23: 16] into SPIS req01[23:16 11'b1, 7 107, 8 h011 // put bus write data [31: 24] intO SFIS reg01[31:24] 11'bl, 7 h08,8 h04)// put bus address [7: 0] into SPTS regC2[7: 0 7 h09,8 h001 // put bus address [15: 8] into SPIs reg02[15: 8 H1 bl, 7 h0A, 8 h13)// put bus address [23: 16] into SPIs reg02[23: 16 1′b1,7′aB,8′h10}// put bus address[31:24] into spis rea02[3-:24] 1′b1,70C,(3′b0,1′b0,1′b0,2′310,1b1}}// Start the bus write access via rbus masser interface Step3 Wait for the bus accessing to be done. spl master asserts following data on SPl_ MOSI: [ b0, 7h10, 8 hxx)// Read sPis bus interface status Wait until the SPl MISo returned data bit[o]=0, and make sure that either rbus or pbus finishes the bus access 2) Example 2: Read 0X0123 4567 data from the register at address 0x1013-0004 Step 1 Check if SPIS is idle. SPI master asserts following data on SPl MOSI b0,7′210,8′hxx}// Read SPIs status reg04 Wait until the SPl_ MISO returned data bit[o]=0, which indicates the Rbus/Pbus interface of Spis is idle and ready to execute a new access command C 2015-2017 Mediatek Page 3 of 12 his document contains information that is proprietary to Media tek Inc. ("Media tek")and/ or its licensor(s) Any unauthorized use, reproduction or disclosure of this document in whole or in part is strictly prohibited MediaTek mt7688 SPI Slave MEDIATEK Labs(② Programming guide Step2 Prepare commands for bus accessing. SPl master asserts following data on SPl_ MoSi respectively 11 b1, 7'h08,8h04)// put bus address [7: 0] into SPIS regC2[7: 01 H1'bl, 709, 8) / put bus address [15: 8] into SPIS reg02[15: 8. [1 bl, 7 h0A, 8 h13)// put bus address [23: 16] into SPis reg02[23: 16 1′b1,7′0B,8′h10}// put bus address31:24] into sPis rea02[31:24 1′b1,7′20c,3′b0,1b0,1b1,2b10,b0}}// start the bus read access via pbus masser interface Step3 Wait for the bus accessing to be done SPl master asserts following data on SPI MOSI {1b0,7′10,8′hxx}// Read spis status Wait until the SPl MISO returned data bit[o]=0, and make sure that either rbus or pbus finishes the bus access Step4 Get read data. SPI master asserts following data on SPl_ MOSi respectively 7'h00,8'hxx// get bus read data [7: 0] from SPIs reg00[7: 01 SPIS MISO return data 16 hxx 67 {1′b0,7′a01,8′hxx}// get bus read data[15:8] from SPIS reg00[15:8] SPIS MISO return data 16 hxx 4 1′b0,7′02,8′hxx)// get bus read data[23:16] from SPIs reg00[23:16] SPIS MISO return data 16'hxx 23 11 bo,7003,8'hxx)// get bus read data [31: 24] from SPIs rego[31: 24] SPiS MISO return data 16 hxx 01 1.3.2 Sequential mode 1)Example 1: Write 0x0123 4567 data to the register at address ox1013_0004 Step1 Check if SPIS is idle. SPI master asserts following data on SPI MOSI 1′b0,7′10,8′h00}// Read spis bus interface status Wait until the SPl MISO returned data bit[o]=0, which indicates the rbus/pbus interface of SPis is idle and read to execute a new access command Step2 Prepare commands for bus accessing sPl master asserts following data on SPl_MOSI 1′b1,70<,8′h67,sh45,8′h23,g"h01,8h04,g"h00,8h13,8′h10 3′b0,1b0,1′b0;2′b10,1′b-} / put bus write daca[31: 0] into SPIs reg01[31: 01, put bus address [31: 0] into SPIs reg02[31: 0 // start the bus write access via Rbus master interface Step3 Wait for the bus accessing to be done SPi master asserts following data on SPI MOSI 11 b0, 7010,8 h001//Read sPIs bus interface status Wait until the SPl Miso returned data bit[o]=0, make sure that either rbus or pbus finish the bus access. C 2015-2017 Mediatek Page 4 of 12 his document contains information that is proprietary to Media tek Inc. ("Media tek")and/ or its licensor(s) Any unauthorized use, reproduction or disclosure of this document in whole or in part is strictly prohibited MediaTek mt7688 SPI Slave MEDIATEK Labs② Programming guide 2) Example 2: Read 0x0123 4567 data from the register at address 0x 10130004 Step Check if SPIS is idle. SPI master asserts following data on SPl MOSI 11 b0, 710, hxx)// Read SPIS status reg04 Wait until the SPl- MiSo returned data bit[o]=0, which indicates the rbus/ pbus interface of spis is idle and ready to execute a new access command Step2 Prepare commands for bus accessing sPl master asserts following data on SPl MOSI 1"b1,708,8′h04,sh00,8h13,s′h10,[37b0,1rb0,1b1,2b10, 1′10 // put bus address [31: 0] into SPIs reg02[31: 01 // Start the bus read access via pbus master interface Step3 Wait for the bus accessing to be done. SPl master asserts following data on SPl_MOSI {1b0,7′10,8′hxx}// Read sPis status reg04 Wait until the sPl MiSo returned data bit[o]=0, make sure that either rbus or pbus finish the bus access Step4 Get read data spi master asserts following data on SPl MOSI 1′b0,7200,8′hxx,8hxx,8′hxx,8′hxx:// get ous read data from SPIS reg00[31:0 SPIS MISO return data[8'hxx, &h67,8h45, &h23, 8'h011 1. 4. Protocol Timing Limitation: Maximum clock frequency: 20MHz C 2015-2017 Mediatek Page 5 of 12 his document contains information that is proprietary to Media tek Inc. ("Media tek")and/ or its licensor(s) Any unauthorized use, reproduction or disclosure of this document in whole or in part is strictly prohibited MEDIATEK Labs② MediaTek mt7688 SPI Slave Programming Guide SCK CPOL=-HHHHHH SS Cyde#_12345X6X78 CPHA=0 MISO Z123450607802 MOSI Z1234567080Z Cycle #1234506 78 CPHA=1 MISO 201223456782 MOSI Z1 4X5X6 8 1. 4.1. CPOL=0. CPHA=0 SPIS Write Mode CPol=0/CPHA=0 16 bits SPI CK SPI MOS XXX W A6 A5 A4 A3 A2A1 A0 D7 D6 D5 D4 D3D2 D1DO SPI MISO XXX SPIS Read Mode CPol=o/CPHA=o SPI CS sP几几 SPI MOSI XXX R AG A5 A4 A2 AO XXX SPI MISO D7 D5 D4 D2 cad data 8-bits- c 2015-2017 Media tek inc Page 6 of 12 his document contains information that is proprietary to Media tek Inc. ("Media tek")and/ or its licensor(s) Any unauthorized use, reproduction or disclosure of this document in whole or in part is strictly prohibited

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