R820T_register_description_datasheetR820T寄存器描述文档，网

文件名称: R820T_register_description_datasheet

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详细说明：R820T寄存器描述文档，网上很难找到R820T的寄存器信息。Rafael Micro Write Mode When the slave address matches the l2c device id with write control bit, 1 'c start interprets the following first byte as first written register address. These following bytes are all the register data (page write I c control). Register 0 to Register 4 are reserved for internal use only and can be written by I"c write command Figure 1-1: The Typical Write Mode Sequence S Ex: 00110100/A Register t chip ID, Oy Address A (Reg. Address)/A Data Data A(Req. Address+2) A Reg. Address+1) P s: From Master to Slave A: Acknowledge(SDA low) S: Start p A NO Acknowledge(SDA high) Figure 1-2: An Example of Write Mode Procedure SCL ⊥L山L山山儿山山HHH凵」凵凵山L凵 SDA <下 S00110100A000 Reglster Address1(4: 01A Daa1[7: 0] A AA P CONFIDENTI o 2012 by Rafael Microelectronics, Inc. All rights reserved Rafael Micro Read mode When the slave address matches the Ic device ID with read control bit, data are immediately transferred after ack command. Reading data transmission begins from core register 0 to final register until"P"(STOP)occurs. The data is transmitted from LSB to MSB, and the data of register 0(0x96)is fixed as reference check point for read mode Figure 1-3: The Typical Read Mode Sequence s Chip ID, OJ ata in Data in Data in Data in Ex:00110101 A Register1A Register 3 A A/A P egister 0 Register 2 s: From Master to Slave A: Acknowledge(SDA low) Start top A NO Acknowledge(SDA high) Figure 1-4: An Example of Read Mode Procedure SCL FF吧吧吧RR SDA 上「「 s0011 01 Data in Register 0[0:7 A Data in Register 1 7I A Data ir Register 3 [o7 P CONFIDENTI o 2012 by Rafael Microelectronics, Inc. All rights reserved Rafael Micro 1.2 Control Registers Register Configuration Total 32 registers are programmable to set the major functions of R820T2. the register matrix in table 1-2 outlines the structure of register bit. Detail register description is listed in the next section Table 1-2: Register Matrix Reg Reg Write B7 B6 B5 B4 B3 B2 Address//Read 0x00ROR 0 0 0 0 0X01 R1R 0x02 R2R VCO INDICATOR[6: 01 0x03R R RF INDICATOR [7: 0 0X04 R4 R 0x05 R5 W/R PWD LT 0 PWD LNA1 LNA GAIN M○DE LNA GAIN3: 0 0x06 R6 W/R PWD PDET1PWD PDET3FILT_3DB 0 PW LNA[2: 0 0X07 W/R 0 PWD MIX PWO MIXMIXGAIN_MODE MIX GAIN[3: 01 0x08 R8 W/R PWD AMP PWO AMP IMR G[5: 0] 0X09 R9 W/R PWD_IFFILT PW1_IFFILT IMR_P[5: 0 OXOA R10 W/R PWD_FILT PW FILT FILT CODE3: 0 Ox0BR11 W/R FILT- BW[1: 0 HPF[3:0] OXOC R12W/R PWD VGA VGA MODE VGA CODE[3: 0 OxOD R13 W/R LANVTH_H[3: 0 LNAVTH L[3: 0 OXOE R14 W/R MIXVTH H3: 0] MIXVTH L3: 0 OXOF R15W/R CLK OUT ENB 0 CLK_AGC_ENB 0x10 R16W/R SEL_ DIV[2: 0 REF DIV2 CAPX(1: 0 0x11 R17 W/R PW_LDO_AL1 0x12 R18W/R 0 000 PW SDM 000 0 0 0x13R19W/R 0 0 0 0x14 R20W/R s|2c[1:0 N|2C[4:01 0x15R21W/R SDMN[8: 1] 0x16 R22 W/R SDM_N[16:9 0×17R23WR PW_LDO_D[1:0]1 OPEN D 0x18R24W/R 0 0x19 R25 W/R PWD RFFILT 0 SW AGC Ox1A R26W/R RFMUX[1: 0 0 PLL AUTO CLK[1: 0 RFFILT1: 01 Ox1B R27 W/R TF NCH: 0] TF LP[3: 0 Ox1C R28W/R PDET3 GAIN3: 0 0 0 0x1D R29 W/R PDET1 GAIN[2: 0 PDET2 GAIN[2: 0] Ox1E R30W/R PDET CLK4: 0] 0X1F R31 W/R 1000 0 CONFIDENTI o 2012 by Rafael Microelectronics, Inc. All rights reserved Rafael Micro 1.3 Register Index and Description Table 1-3: R820T2 Register Index and Description 匚 RegR/W| Bitmap| Symbol Description Loop through ON/OFF R∧ [7]PWD_LT 1:o斤f LNa 1 power control RM [5] PWD_LNA1 0: 1:0ff R5 0x05 LNA gain mode switch R [4 LNA GAIN MODE 0: auto manua LNA manual gain control [3: 0] LNA_GAIN[3: 0 15:max gain 0: min gain Power detector 1 on/off R∧ [7] PWD_PDET1 0: on 1:o斤f Power detector 3 on/off R∧ [6]PWD_PDET3 0: off 1: on R6 0x06 Filter gain 3db R∧W [5] FILT__3DB 0:0db 1:+3db LNA power control RA [2: 0]PW_LNA(2: 0 000: max 111: min Mixer power R∧ [6] PWD_MIX O: off 1: on Mixer current control R [5]PWO_MIX 0: max current R7 1: normal current 0x07 Mixer gain mode R [4]MIXGAIN_MODE O: manual mode 1: auto mode Mixer manual gain control R∧ 3:0]MXGA|N[3:0 0000->min 1111->max CONFIDENTI o 2012 by Rafael Microelectronics, Inc. All rights reserved Rafael Micro R/ Bitmap Symbol Description Mixer buffer power on/off R [7] PWD_AMP 0: off 1: on Mixer buffer current setting R8 R/ 6 PWO AMP 0: high current 0x08 1: low current Image Gain Adjustment R/ 5:0]MRG5:0 0: min 63:max IF Filter power on/off R/ [7]PWD_IFFILT 0: filter on 1:0f IF Filter current R9 R [6 PW1 FFILT 0: high current 0x09 1:low current mage Phase Adjustment R/ 5:0]IMR_P[5: 0 0:min 63:max Filter power on/off R∧ [7]PWD_FILT 0: channel filter off 1: on Filter power control R10 RN [6:5] PW_FILT[1:0] 00: highest power OXOA 11: lowest powe Filter bandwidth manual fine tune 0000 Widest R/ [3: 0] FILT_CODE[3: 0 1111 narrowest CONFIDENTI o 2012 by Rafael Microelectronics, Inc. All rights reserved Rafael Micro Reg R/Bitmap Symbol Description Filter bandwidth manual course tunnel 00:widest R [ 6: 5] FILT_BW 10 or 01: middle R11 11: narrowest OxOB High pass filter corner control R∧ 3:0]|HPF3:O] 0000: highest 1111: owest VGA power control R PWD VGA 0: vga power off 1: vga power on VGA GAIN manual pin selector R12 R∧W VGA MODE 1: IF vga gain controlled by agc pir OOC O: IF vga gain controlled by vga_code[5: 0 IF vga manual gain control R/ [3: 0] VGA_CODE[3: 0 0000::120dB 111:+40.5dB;-35dB/step LNA agc power detector voltage threshold high setting RW [7: 4] LNA_VTHH14: 0 1111:1.94V R13 0000:0.34V, 0.1∨/step OXOD LNA agc power detector voltage threshold low setting RA [3: 01 LNA VTHL[3: 0 1111:1.94V 0000:0.34V o 1 v/ step MIXER agc power detector voltage threshold high settle R/ [7: 4]MIX_VTH_H[4: 01 1111:1.94V R14 00000.34V,~0.1V/step OXO MIXER agc power detector voltage threshold low setting RN[3: 01MIX_VTH_L[3: 01 1111:1.94V 00000.34V,~0.1V/step CONFIDENTI o 2012 by Rafael Microelectronics, Inc. All rights reserved Rafael Micro Reg R/W Bitmap Symbol Description Clock out pin control R [4] CLK_OUT_ENB 0: clk output on R15 OxO AGc clk control R [1] CLK_AGC_ENB 0: internal agc clock on 1: off PLL to mixer divider number control 000:mixer in=vco out/2 R∧ [7:5]SEL_D[3:0] 001: mixer in vco out/4 010: mixer in vco out /8 1011: mixer in =vco out PLL Reference frequency Divider R16 R REFDIV 0->fref=xtal_freq 0x10 1-> fret=xta freql/2 (for xtal >24MH Internal xtal cap setting 00->no c R/[1: 0]CAPX(1: 0 01->10pF 10->20pF 11->30pF PLL analog low drop out regulator switch 00: off R17 R/ [7: 6]PW_LDO_A[1: 01 01:2.1V X 10:2.0V 11:1.9V PLL integer divider number input Si2c R20 R/ [7:6]S2c[1:0 Nint=4 Ni2c+Si2c+13 0x14 PLL divider number Ndiv=(Nint Nfra)*2 R 5:0]N|2C50] PLL integer divider number input Ni2c R21 R/[7: 0] SDM_IN[ O1 PLL fractional divider number input SDM[16: 11 0x15 Nfa=sDM_N[16}24-1+SDMN[15]2^2+…+SDM_N[2] R22 [7:0]sDM_|NZ。 2~15+ SDM IN[1]2~16 0x16 CONFIDENTI o 2012 by Rafael Microelectronics, Inc. All rights reserved Rafael Micro Reg R/ Bitmap Symbo Description PLL digital low drop out regulator supply current switch 00:18V8mA R 76] PW LDO DI1:0]01:1.8V4mA R23 10:2.0V,8mA 0x17 11: OFF Open drain R/ [3] OPEN_D[3] 0: High-Z 1: LOW-Z RF Filter power R/ [7] PWD_RFFILT 0: off R25 1: on 0x19 Switch agc_pin R∧ [4] SW_AGC 10: agc=agc in 1: agc=agc in2 Tracking Filter switch R/W [7: 6] RFMUX[1: 0 00:TOn 01: Bypass PLL auto tune clock rate PLL_AUTO_CLK[1 00: 128 KHz R26 R/ [32] 0 01:32kHz OX1A 10: 8 kHZ RF FILtER band selection 00: highest band R∧ [1 RFF‖LT1:01 01: med ba 10: low band R27 RW【7:4] TF_NCHD1:0] 0000 highest corner for LPNF, 1111 lowerst corner for LPNF 0X1B R/ 3:0]TFLP30] 0000 highest corner for LPF: 1111 lowerst corner for LPF Power detector 3 ToP(take off point) control R28 0: Highest RW【7:4]PDET3GAN10] OXiC 15: Lowest CONFIDENTI o 2012 by Rafael Microelectronics, Inc. All rights reserved

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