AN-TW8835 HADC & Measurement v0.1.pdftw883

文件名称: AN-TW8835 HADC & Measurement v0.1.pdf

所属分类: 硬件开发

开发工具:

文件大小: 463kb

下载次数: 0

上传时间: 2019-10-31

提供者: ma5****

下载 (463kb)

不能下载？报告错误

详细说明：tw8835的说明文档，官方给的，大家可以看看，感觉还是有用的SYNC Processor Depending on video source there are three different type of sYNc format. ∧. SOG/SOY (Analog) u11几几几11 CSYNC Digital) ∥uL几几几n1 HSYI VSYNO Figure 3 SYNC Type H/V separated SYNc is the basic SYNc and is mostly used PC RGB input. CSYNC(Composite SYNC)is combined by H/V SYNC in digital level and is used at some of GPs module to reduce interface ping SOG/SoY is a SYNC imposed in Green or Y signal and commonly used in component video SYNC Processor separates h/VsYNc from CSYNc and in case of interlaced input, Field information is provided VSYNC U +VSYNC OUT> Clamping Slice Level SYNC U Separator HSYNCOUT> CSYNC HSYNC Figure 4 SYNC Processor 1. Composite SYNC When the SYNc is Composite, it has to be separated to Hsync and vsync through sYNc Processor. when the input is standard component video such as 480i/p, 576i/p, 720p, 1080i/p the syNc processor can extract pure H/VsYNC from CSYNc by eliminating serration pulsed. But it may not work correctly for non-standard inputs and the uneven HSYNc period should be masked before input to PLL. the masking period is set by COAST and during coAST period the LLPll runs as free run not to be far off from regular period During COAST period, the LLPLL output clock is similar to the regular clock, but it is not exactly same and it takes some time to get stable clock after the COAST period. The recovery should be done during blanking period not to make wrong video sampling. So minimum COAST setting is needed to give LLPLL enough recovery time. CSYNC 1nn几}1111 NSYNC (HSYNC) (COAST) Pre-Coastl I Post-coast Figure 5 CSYNC and COAST intersil l Techwell Register Index Description 1CB[5] Enable coast 1C9[7:0] Pre-COAST Masking period before VcYNc 1cA7:0 Post-COAST Masking period after VSYNC 2. SYNC On Green /Y If the composite SYNC comes from SOG/soY, it should be converted to digital before going through SYMC Processor. Through a capacitor, the signal is Ac coupled and dc is restored by clamping. The clamping makes the lowest level to ground level, which means that the sYNc tip will be oV. After the clamping by slicing SYNC level, CSYNc can be extracted. The slice level can be adjusted by changing comparator threshold Register Index Description SoG Slicer Threshold 1CB[40 10mV per step The value equals to 330mV and increasing the value decreases 10mV per step. Maximum value 31 equals to 10mv VDD 1.0V 1.0V Before Clamping After Clamping After Slicer Figure 6 SoG/soY clamp and slicer 3. Input Detection SYNC Processor also provides input status detection functions. It includes H/VSYNc input, polarity, and input standard format. Register Index Description 1c1[3] Composite SYNC Detection 1c1[4] HSYNC Detection 1c15] VSYNC Detection 1c16] HSYNC P。|arit 1C17] VSYNC Polarity Input Format Detection This works for only csYNc input 0=480i 1c1[20] 1=576i 2=480p 3=576p 4=108 5=720 6=1080p 7=none NOTE: The standard detection is valid for only composite sYNc input case. A intersil l Techwell Line-LOCK PLL Since there is no clock signal in component video and Pc analog RGB, the ADc sampling clock has to be generated based on HSYNC. LLPLL generates pixel clock by multiplying divider to HSYNc input. It also provides 32 step phase adjustment to get proper sampling position depending on analog data and HsYnc delay. 匚27MH PLL CP 0x1CDE 6 I (×4)LP01CD6541 108MHZ Ibias HSYNC COAST DPLL DAC PLL Clock (x8) Coast Enable Divider 27MHZ /21135Ht VcO[0×1C2154 x1C330 0x1E061 VCORst0×1Eo71 [0×1cB5 0x1C40 CP CP Fine0×1E054 se 0x1C5[4: 01 0×1cD3:2l Loop On [Ox1C671 LP 5pF 0x1EOC 01 Gan×1c664 Filter×1c6[20 Figure 7 LLPLL -LPLL in TW8835 is composed of two analog Pll and one digital PLL X4 PLL generates 108MHz with 27 MHz system clock by multiplying 4 and passes it to digital PLL. Digital PLL is a Line-Lock PLL which generates clock locked in input hsyNc but the frequency is eight times slower than expected clock X8 Pll generates eight times clock with Digital PLL output Register Index Description DPLL feedback divider value 1c33:0]c4[7:0] Output frequency is Hfreq x Feedback Divider Phase AdJustment 1c5[4:0] 32 ste vco Range selection for x& PLL 1C2[5:4] 0=5~27MHz1=10~54MHz2=20~108MHz3=40~216MHz 1c2[20] Change Pump current selection for X8 PLL 1c6[6:4] DPLL Loop Gain control DPLL Loop Filter control Lower value shows faster response time 1c6[20] Higher value shows slower response time, but better jitter performance To get the best performance and response time, Initially seto and wait until the pll is stable and then change it to 7 1 HSo Input HSYNc cannot be used as is for scaler input, because depending on the clock phase, the hsync position can be one clock earlier or later. This affects scaler reference timing and can be shown as horizontal jitter. so the input HSYNc should be regenerated based on LLPll clock to provide correct hSYNc and clock timing to scaler tW8835 LLPLL provides Hso for this purpose. Hso transition always follows clock falling edge to give maximum timing margin intersil l Techwell Input Hsync Clock Phase o HSO Clock Phase180° ure 8 HSo Register Index Description HSYNC Output selection 1CC32] 0= HSO 1=Debug 2=HSYNC Pin 3=CS PAS HSO is recommended. others are test purpose 1Dc[5:0] Hso width intersil l Techwell ADC W8835 AFE (Analog Front End) has two different operation modes. One is decoder mode, which is 27MHz free- run sampling mode, and the other is High speed Mode which is line-lock sampling mode for component and analog rgB input. Maximum sampling frequency is up to 165MHZ, which can cover up to 1080p(1920X1080)or UXGA (1600X1200)60HZ. The high speed mode operation is described in this section 1 Input Mux YiN has up to 4 inputs ciN has 2 inputs and vin also has up to 2 inputs. but as shown in figure 9, yiN2 shares the pin with SoG1, and Yin3 shares the pin with vin1 and Yout. when yin3 or vin1 is used, yout has to be disabled to avoid the signal confliction YINO Clamping IN 1 PGA ADC 10bit YN2/SOG1 Clamping+ OUT YIN3/IN1 Clamping CIN 1 PGA CIN2 ADC 10bit Clamping+ Clamping+ VINO PGA ADC 10bit lamping SOGO SOG Figure 9 ADC in HS mode Register Index Description 「10232 YIN selection 102[7102(1 CIN selection 102[0] viN selectlon 105[5] Disable yout AFE Mode selection 105[0 AFE includes PGa and clamping 0= RGB 1= Decode 2. Clamping Clamping is restoring dc level of the video signal. The dc level of input signal is cut by clamping capacitor and the dc level is restored by clamping circuit as Figure 10 clamping to set the signal level in ADc voltage reference intersil l Techwell ADC C g Logic VREFT vcoM卜- mmmmm VREFB RG/B Before Clamping After Clamping Figure 10 Clamping PC analog RGB input requires bottom level(black level) clamping for all R/G/B signals and component video requires bottom level clamping for Y and center level clamping for Pb and Pr signal Clamping Position Control T BP Input video HSO (2)1(3) (1 Hso delay from input Fixed(about 0.4usec (2) Position Offset for Clamp Evaluation Period, Pulse Start/ stop Unit is 27MHz clock (37nsec) (3 Clamp Pulse Start UnIt Is 27MHz clock(37nsec) (4 Clamp Pulse Stop. Unit is 27 MHz clock ( 37nsec) (5 Clamp Evaluation Period. Fixed (about 3.Usec Get average value during this period to get clamp reference value. (6 Clamp Pulse Width=(4)- 3) Figure 11 Clamping Position During (5), clamping level is evaluated and if it is lower than reference level, Up Pulse is generated during(6 and if it is higher, Down Pulse is generated to keep the level same as reference To get correct clamping operation, both clamp Evaluation Period(5)and clamp Pulse(4)should be in blank period (Back Porch) THS Min position s 11 0. 037usec THS+ TBP Max position≈ 19 0. 037usec In case of RGB there is no sYNc in video signal, so the Min position can be 0 8 intersil l Techwell Register Index Description 1D4[2:0] Disable clamping E3[30] ClampX2 current control 1D4[4] Disable clampX2 for Y input 1D4[3] Disable clampX2 for U/V input Clamp Mode 1D4[7] 0= Manual 1= RGB Auto(level 16) Manual mode is recommended since auto mode level is too high Clamp level control 1D9. 1DA 1DB 41 for rgb and y. 128 for u and v is recommended 1D5[7:0 clamp Pulse start 067:O Clamp Pulse Stop 1D7[7:0] Posltion Offset for Clamp Pulse and Evaluatlon 1D4[5] SYNC Edge Selection for Clamp reference 0=- Falling 1- Rising AFE Mode selection 05[0] 0= RGB 1= Decoder Should be ' for RGB/Component input mode 1E24:0 Analog clamping level Dc bias level when clamping is disabled 3. vREf and Gain ADC voltage reference and gain are programmable. But it is recommended to use default vreF (Vrefb=200mv, Vcom=700mv, Vreft=1200mv, when VDD is 1.8V), which is 1.0Vp-p If input level is lower than full scale, it is recommended to amplify to 1. 0vp-p by PGA rather than controlling VREF. PGa provides 6dB to- 3db gain with gbit control, which can cover input Vp-p range 05.v-1 4V. the gain vs the register control is plotted below Figure 12 2.0 1.8 1.6 之 1.4 1.2 1.0 0.8 0.6 0 100 200 300 400 500 Gain Code d<8: 0> Figure 12 Gain vs Register For the standard input level (0.7vp-p active video level), the gain is 1.43or20lo 3.1dB, which is about 277 (Ox115)in register value. In this range, the gain per step is about 0.0026 In the real system implementation, the input video level will be affected by many variables such as input source itself, cable intersil l Techwell and termination and power supply so to get full scaling ADC with certain system, gain calibration is recommend using input measurement function for every system Register Index Description PGA Selection 1E65] 0= Low Speed PGA 1= High Speed PGA There are two individual PGAs in AFE set for high speed operation VREF Selection 1E26:5] 0=0.8V 1=0.9V 2=1.0V 3=1.1V Internal ADC Reference voltage. Use 1.0v. others are test only. 1E3[6:4] Bias current control for vref Use default 1E4[6:4] Bias current control for Sample and hold Use default LE4[2:0] Bias Current control for ADC Amplifier Use default 1E56:4 Bias current control for PGA Use default 1E5[2:0] Bias Current control for input Buffer Use default Bias Current control for whole aFe Use default 1E2[7 0= Normal 1=Half of normal Boost vref 1E53] Set for High Speed operation It consumes more power Y channel Adc gain 1D[2],1D1[7:0] 0=3dB~511=6dB U channel abc Gain 1D0[1,1D2[7:0] 0=3dB~511=6dB 1DO[o],1D3[7:0] V channel ADc Gain 0=3dB~511=6dB 0 intersil l Techwell

(系统自动生成,下载前可以参看下载内容)