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文件名称: BCM43526 5G WiFi IEEE 802.11ac Draft 2 × 2 Dual-Band Single-Chip Datasheet
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  上传时间: 2019-10-31
  提 供 者: zhangbao********
 详细说明:BCM43526 5G WiFi IEEE 802.11ac Draft 2 × 2 Dual-Band Single-Chip DatasheetBCM43526 Advance data sheet Table of contents Table of contents About this document Purpose and Audience Acronyms and abbreviations.................. :.:::.::. Technical Support........................ Section 1: Introduction Section 2: Functional Description G|oba| Functions…………… 78999 Power Management Voltage regulators.... 9 Reset GP|O| nterface..…… OTP .·::· 10 SPROM Interface(optional) 10 JTAG Interface 10 Crystal Oscillator............ 自,非t自非自自曲自。自非曲着自。自音音 ·:.:··:::·:·:::·:::·:·:: 10 USB 2.0 Device Interface 12 Serial flash interface 14 IEEE 802.11ac Draft MAC Description lEEE 802.11ac Draft Dual-Band radio transceiver 17 Receiver path Transmitter path 7 Ca| ibratⅰon. a::.::::: 117 Section3: Pin Assignments…,,,,…, n…18 BCM43526 QFN Pin Assignments 19 Signals by pin Number…………….…… 20 Section 4: Signal and Pin Descriptions meemeeedoaoeeoeenooo 22 Package signal Descriptions 22 Strapping Options… :.:...:.:::::.:.:.::.::::: 27 Section 5: electrical characteristics 28 Absolute Maximum Ratings Recommended Operating Conditions and DC Characteristics 29 Current Consumption 29 BROADCOMo Aprl13,2012·43526-DS100-R Page 3 5/7/20120LaR BCM43526 Advance data sheet Table of contents Section6: RF Specifications,,,,,…,,,……,…30 Introduction 30 24 GHz Band General RF Specifications…,,,…,… 31 WLAN 2. 4 GHz Receiver Performance Specifications 32 WLAN 2. 4 GHz Transmitter Performance Specifications 37 WLAN 5 GHz Receiver Performance specifications 38 WLAN 5 GHz Transmitter Performance Specifications General Spurious Emissions Specifications ··:::::::.:··:::·:·::::::::::.::·::.· 41 Section7;: Timing Characteristics…,,…,,…,…,…,…,…,…,…,…42 Power Sequence Timing 42 SPROM Timing Diagran… 43 Section 8: Thermal Information 44 jDEC Thermal characteristics wwwwwwwmwwwwwwwwo.... 44 Junction Temperature Estimation and PST Versus Thetajc 44 Section 9: Package Information . Ordering Information :..:.::a 46 BROADCOMo Aprl13,2012·43526-DS100-R Page 4 5/7/20120LaR BCM43526 Advance data sheet List of figur List of Figures Figure 1: BCM43526 Block Diagram..... igure 2: MIMO System Diagram Showing 2 X 2 Antenna Configuration 188 Figure 3: BCM43526 Functional Block Diagram Figure 4: Recommended Oscillator Configuration 1 Figure 5: USB 2.0 Device block Diagram 13 Figure 6: Enhanced MAC Block Diagram 15 Figure7:108Pin(12×12) QFN Package… 9 Figure 8: Port Locations ,30 Figure 9: Power-Up sequence Timing Diagram 42 Figure 10: SPROM Timing Diagram 43 Figure11:BCM43526108Pin(12×12) Mechanica| Drawing………………………………45 BROADCOMO Aprl13,2012·43526-DS100-R Page 5 5/7/20120LaR BCM43526 Advance data sheet List of tables List of tables Table 1: Crystal Oscillator Requirements...... 10 Table 3: Signal Descriptions. 22 Table 4: Strapping Options 27 Table 5: Absolute Maximum Ratings 28 Table 6: Recommended operating Conditions and dc characteristics 29 Table 7: BCM43526 Current Consumption 29 Table 8: 2.4 GHz Band General RF Specifications 31 Table 9: WLAN 2. 4 GHz Receiver Performance Specifications.... 32 Table 10: WLAN 2.4 GHz Transmitter performance specifications 自自自 1, 37 Table 11: WLAN 5 GHz Receiver Performance Specifications 38 Table 12: WLAN 5 GHz Transmitter Performance Specifications. ......................................................41 Table 13: General Spurious Emissions Specifications....................... 41 Table 14: Power-Up Timing Parameters.... 42 Tabe15: SPROM Timing.…..…..….….….….….….….…………………………………43 Table 16: JEDEC Thermal Characteristics, 12 x 12 Package 44 Table 17: Ordering Information 46 BROADCOMO Apri13,2012·43526-Ds100-R Page 6 5/7/20120LaR BCM43526 Advance data sheet About this document About This document Purpose and Audience This data sheet provides details about the functional, operational, and electrical characteristics of the Broadcom BCM43526. It is intended for hardware design, application, and OEM engineers Acronyms and Abbreviations In most cases, acronyms and abbreviations are defined on first use for a comprehensive list of acronyms and othertermsusedinbRoadcomdocumentsgotohttp://www.broadcom.com/press/glossary.php Technical Support Broadcom provides customer access to a wide range of information, including technical documentation schematic diagrams, product bill of materials, Pcb layout information and software updates through its customersupportportal(https://support.broadcomcom).ForaCspaccountcontactyourSalesorEngineering support representative In addition, Broadcom provides other product support through its Downloads Support site (http://www.broadcom.com/support/) BROADCOM Apr13,2012·43526-DS100R Page 7 5/7/20120LaR BCM43526 Advance data sheet Introduction Section 1: Introduction The BCM43526 is the latest innovative chip from Broadcom and is based on IEEE 802.lac Draft. The chip is designed to take current WLAN systems to the next level of higher performance and greater range with Multiple Input Multiple Output(MIMo ) technology, as shown in Figure 2. IEEE 802. 1lac Draft more than doubles the spectral efficiency compared to that of current ieee 802.11a/g WLANs BCM4352 BCM4352 RE RF 2.4/5 GHZ Switches Switches 24/5GH Radio Radie Host80211ac MAC/PHY with with 80 Integrated Each antenna on each device transmits and receives to/from all Integrated three antennas on the peer device. For clarity the blue lines PA a has Tx/Rx ntennas Cand D. The lines of communicaticn however run from all antennas to the two antennas on the peer device. Figure 2: MIMo System Diagram Showing 2 x 2 Antenna Configuration Employing a native 32-bit bus with direct memory access(DMA)architecture, the bCm43526 offers significant performance improvements in both transfer rates and cPu utilization Figure 3 shows a block diagram of the device (default) nterface Fei clock RF SG ANTENNA COREO 802.11ac 802.11ac 2.4/5GHz Radio 26.ANMA—二 MAC FA SG COREO- CA SG CORE1- CUKE High-Spee USB 2.0 RE GPIO ntrols(12) SPRON DISABLE Device Control -USB 2.0 HOSt P SROM CS Figure 3: BCM43526 Functional Block Diagram BROADCOM Apr13,2012·43526-DS100R Page 8 5/7/20120LaR BCM43526 Advance data sheet Functional description Section 2: Functional Description Global functions Power Management The bCm43526 has been designed with the stringent power consumption requirements of battery- powered hosts in mind. All areas of the chip design were scrutinized to help reduce power consumption Silicon processes and cell libraries were chosen to reduce leakage current and supply voltages Additionally, the BCM43526 includes an advanced Power management Unit(PMU). The pmu provides ignificant power savings by putting the bCM43526 into various power management states appropriate to the current environment and activities that are being performed the power management unit enables and disables internal regulators, switches, and other blocks based on a computation of the required resources and a table that describes the relationship between resources and the time needed to enable and disable them Power-up sequences are fully programmable Configurable, free-running counters in the pmu are used to turl on/off individual regulators and power switches. clock speeds are dynamically changed (or gated altogether) for the current mode. Slower clock speeds are used wherever possible Voltage Regulators Two Low-Dropout(LDO)regulators are integrated into the bcm43526: RFldo and the pa vref ldo Reset A power-on or hard reset is initiated by an active low reset pulse on the perst I Schmitt-triggered input pin. A 50 ms low pulse is recommended to guarantee that a sufficiently long reset is applied to all internal circuits including integrated PHYs. The initialization process loads all pin configurable modes, resets all interna processes, and puts the device in the idle state. during initialization the clock source input signal must be active, and all power supplies to the device(3. 3V, 1.8V when applicable, and 1. 2v)must be stable GPIO Interface There are 12 General-Purpose l/o(GPio) pins provided on the 12 x 12 package. GPlOs 8-11 are dedicated whereas GPIOs 0-4 are multiplexed with the JTAG signal functions, GPlo 5 is multiplexed with the power-On Reset, and GPlOs 6-7 are multiplexed with the UART signal functions. These pins can be used to attach to various external devices. Upon power-up and reset, these pins become tristated. Subsequently they can be programmed to be either input or output pins via the plo control register a programmable internal pull-up/ pull-down resistor is included on each GPIO. If a GPlO output enable is not asserted, and the corresponding GPIO signal is not being driven externally, the gpio state is determined by its programmable resistor. BROADCOM Apr13,2012·43526-DS100R Page 9 5/7/20120LaR BCM43526 Advance data sheet Global functions OTP The BCM43526 contains an on-chip One-time Programmable(OTP)area of 6 kbit that can be used for non volatile storage of WLAN information such as a MAC address and other hardware-specific parameters. SPROM Interface(Optional) Various hardware configuration parameters may be stored in an external SPRoM instead of OTP. The SPROM is read by system software after device reset. In addition, customer-specific parameters may be stored in SPROM, depending on the specific board design The 4-wire SPROM interface supports 4 Kbit serial SPROMs by default. It also supports 16 Kbit serial SPROMs with the strapping option JTAG Interface The BCM43526 supports the IEEE 1149.1 JtAG boundary-scan standard for testing the device packaging and PCB manufacturing Crystal Oscillator Table 1 lists the requirements for the crystal oscillator. Table 1: Crystal Oscillator Requirements Parameter Value Frequency 40 MHz(default)or 20 MHZ Mode AT cut, fundamental Load capacitance 12 pF ESR 50Q maximum Frequency stability ±10 ppm at25°C aging ±3ppm/ year max first year,±1 ppm thereafter Drive level 200μ W maximu Shunt capacitance <5 pF BROADCOM Apr13,2012·43526Ds100-R Page 10 5/7/20120LaR
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