驱动光耦316J资料.pdf驱动光耦316J资料pdf,驱动光耦316J资料HCPL31 6J Pr

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详细说明：驱动光耦316J资料pdf,驱动光耦316J资料HCPL31 6J Product Overview Description Two lighL einiLling diodes and two integrated circuits The HcPl-316 is a highly integrated power control housed in the same so-16 package provide the input device that incorporates all the necessary components control circuitry, the output power stage, and two for a complete, isolated iGBT gate drive circuit with optical channels. The input Buffer IC is designed on a fault protection and feedback into one $o-16 package. bipolar process, while the output Detector IC is TTL input logic levels allow direct interface with designed manufactured on a high voltage BiCMos/ microcontroller, and an optically isolated power output Power DMOS process. The forward optical signal path stage drives IGBTs with power ratings of up to 150a as indicated by LeDl, transmits the gate control signal and 1200V.a high speed internal optical link The return optical signal path, as indicated by leD2 minimizes the propagation delays between the transmits the fault status feedback signal. Both optical microcontroller and the IGBT while allowing the two channels are completely controlled by the input and systens to operate at very large coInInon node vollage oulpul ICs respeclively, making the internal isolation differences that are common in industrial motor drives boundary transparent to the microcontroller. and other power switching applicaLions. An oulpul IC provides local protection for the igbt to prevent Under normal operation, the input gate control signal damage during overcurrents, and a second optical link directly controls the iGbt gate through the isolated provides a fully isolated fault status feedback signal output detector IC. LED2 remains off and a fault latch for the microcontroller. A built in "watchdog"circuit in the input buffer IC is disabled. When an IGBT fault monitors the power stage supply voltage to prevent is detected, the output detector IC immediately begins IGBt caused by insufficient gate drive voltages. This a"soft" shutdown sequence, reducing the IGBt current ntegrated igBt gate driver is designed to increase the to zero in a controlled manner to avoid potential IGBt performance and reliability of a motor drive without damage from inductive overvoltages. Simultaneously the cost, size, and complexity of a discrete design this fault status is transmitted back to the input buffer IC via LED2, where the fault latch disables the gate control inpuT and the acLive low fault oulput alerts the microcontroller During power-up, the Under voltage Lockout (UVLO) feature prevents the application of insufficient gate voltage to the iGBt, by forcing the HCPL-316's output low. Once the output is in the high state, the DESAT (ce detection feature of the HCPL-316J provides IGBT protection. Thus, UVLo and DESat work in conjunction to provide conslant IGBT prolecTion VlED1+ VLED1 INPUT IC N LED1 fAD VI UVLO R O DESAT Vc DESAT SHIELD EE LED2 VE RESET。5 FAULT O FAULT SHIELD QUTPUT IC 6章208253PDF用) Page 210 01.5.24, 4: 35 PM Adhe P ageM aker 6.0upPC HCPL31 6J Package Pin Out 7V 1 Pin Descriptions Symbol Description Symbo Description inverting gate drive voltage [GBT emitter] output oulpul ( our) control input supply voltage Inverting gate drive voltage output LED 2 anode. This pin must be left nOur) control input unconnected for guaranteed data sheet perfo CCl Positive input supply voltage DESAT Desaturation voltage input.When the (4.5Vto55V vollage on DESAT exceeds an internal reference voltage of 7v while the IGBT is on, FAULT output is changed from a high state to a logic low state within 5 us. See Note 25 GNDI Input Grounld Vcc Positive output supply voltage. RESET FAULT reset input a logic low input Collector of oulput pull-up triple for at least O l us, asynchronously darlington transistor. It is connected resets FAULT output hig to Vcc directly or through a resistor enables VIN Synchronous control of to limit output turn-on current RESET relative to VIN is required RESET is not affected by uVlo Asserting RESET while Vor is higl FAULT Fault output FAULT changes from a Gale drive vollage output high impedance state to a logic low output within 5 us of the voltage on the DESaT pin exceeding an internal reference voltage of 7 V FAULt output remains low until RESET is brought low. FAULT output is an open collector which allows the FAULT outputs from all HCPL-316Js in a circuit to be connected together in a"wired OR" forming a single fault bus for interfacing directly to the micro-controller LED I anode. This pin must be left Output supply voltage sheet performance. (For optical coupling testing only LEDI LED I cathode. This pin must be connected Lo ground 6-211 6章208253PDF用) Page 21 01.5.24, 4: 35 PM Adobe P ageM aker 6.0JPPC HCPL31 6J Ordering Information Specify Part Number followed by Option Number (if desired) Example: HCPL-316JtXXX No Option= 16-Lead, Surface Mt package, 45 per tube. 500= Tape and Reel Packaging Option, 850 per reel Option data sheets available. Contact Agilent Technologies sales representative, authorized distributor, or visit ourWebsiteatwww.agilent.com Package Outline Drawings (1270) 16-Lead surface mount 1日 dimensions int nches → TYPE NUMBEF DATE CODE meters A316J Yyww 4- 0295±0.010 nOTE. 1234 NITIAL AND CONTINUED VARIATION IN 0406±0.01 THE COLOR OF THE HCPL-316JS WHITE 10312±0254) MOLD COMPOUND IS NORMAL AND DOES (8.966±0254) EADS NOT AFFECT DEVICE PERFORMANCE OR COPLANAR RELIABILITY 0.138±0.005 0.008±D.003 _0.025MN STANDOFF (10.160±0254) Package Characteristics All specifications and figures are at the nominal (typical] operating conditions of Vccl=5V, VCC2-VEE=30 V, VE-VEE=0v, and TA=+25C Parameter Symbol Mi yP Max Units Test ConditionsNote Input-Output Momentary 3750 Vrms RH <50%, t= l min.. 1.2 Withstand voltage TA=25°C Resistance (Input-) RI-o VIo=500 Vdc Capacitance (Input-Output 1.3 F f=1 MHz Output Ic-to-Pins 9 &l0 30 °C/w TA=100°0 Thermal resistance Input IC-to-Pin 4 Thermal Resistance 60 Maximum Solder Reflow Temperature Profile △T=145°,1c/sEc 00006000000 △T=115°c,03c/SEc △T=100°c,15°csEc TIME-MINUTES NOTE: USE OF NON-CHLORINE ACTNVATED FLUXES IS RECOMMENDED 6-212 6章208253PDF用) Page 2 01.5.24, 4: 35 PM Adhe P ageM aker 6.0upPC HCPL31 6J Regulatory Information The HCPL-316u is pending approval by the following Recognized under UL 1577. component recognition organizations program, File E55361 VDE CSA Approved under VDE0884/06.92 with VIORM=891 Approved under CSa Component Acceptance Notice Vpeak #5. file ca 88324 VDE 0884 insulation characteristics Description Symbol Characteristic Unit Installation classification per DIN VDE 0110/1.89, Table 1 for rated mains vollage s150 VrIns I-I for rated mains voltage s300 Vrms I-II for rated mains voltage s600 vrms I-II Climatic Classification 55/100/21 Pollution Degree (DIN VDE 0110/1.89) 2 MaximuIn Working Insulation Vollage 891 Input lo Oulpul Test Vollage, Melhod b VIORM X 1.875= VPR, 100% Production Test with tu l sec 1670 PEAF Partial Discharge<5 pC Input to output Test voltage, Method a** VIORM X 1.5= VPH, Type and Sample Test, tm =60 sec 1336 Partial Discharge <5 pC Highest Allowable Overvoltage Transient Overvoltage tini=10 sec) 6000 VeAU Safety-limiting values- maximum values allowed in the event of a failure, also see Figure 2 Case Temperature. T 175 Input Powe Ps INPUT 400 mW Output Power S OUTPUT 1200 mw Insulation Resistance al ts Vio 500 V Isolation characteristics are guaranteed only within the safety maximum ratings which must be ensured by protective circuits in application. Surface mount classification is class a in accordance with CECCoo802 Refer to the optocoupler section of the Isolation and Control Components Designer,'s Catalog, under Product Safety Regulations section, (VDE 0884) for a detalled description of Method a and method b partial discharge test profiles 1400 Ps, OUTPUT 1200 Ps, INPUT c800 u.v 600 400 0255075100125150175200 Ts-CASE TEMPERATURE-C Figure 2 Dependence of Safety Limiting Values on Temperature 6-213 6章208253PDF用) Page 213 01.5.24, 4: 35 PM Adhe P ageM aker 6.0upPC HCPL31 6J Insulation and Safety Related Specifications Parameter Symbol valueUnits Conditions MinimuN External Air GapL(101)8.3 Inn Measured froIn input terMinals lo oulpuL (Clearance) terminals, shortest distance through air. Minimum externa L(1O2〕 mn Measured from input terminals to output Tracking(Creepage terminals, shortest distance path along body Minimum Internal plastic 0.5 mm Through insulation distance conductor to Gap (Internal Clearance) conductor, usually the straight line distance thickness between the emitter and detector Tracking Resistance CT >175 Volts DIN IEC 112/VDE 0303 Part l (Comparative Tracking Index Isolation group IIa Material Group (DIN VDE o110, 1/89, Table 1) Absolute Maximum Ratings Parameter Symbol Ⅳin Max Units Note Storage Temperature 55 125 Operating Temperature -40 100 Output Ic Junction Temperature T 125 Peak Oulpul CurrenL 2.5 A 5 Faull Oulput Currenit FAULT 8.0 IIA Posilive Input Supply voltage -0.5 5.5 Volts Input Pin Voltages VIN+, VIN and VRESlT 0.5 Total Oulpul Supply Vollage TVcc2-VEC 0.5 Negative Output Supply volta IVE-VEE 0.5 15 Positive Output Supply Voltage (cc2-VE 0.5 35-VE- VEE) Gate Drive: Output Voltage 0.5 Collector Voltage Vor+5 v DESAT Voltage VDI ESAT VE+10 Output IC Power Dissipation 600 mw Input IC Power Dissipation PI 150 Solder reflow Temperature profile See Package Outline Drawings section Recommended Operating Conditions Symbol Min Max. UnitsNote Operating Temperature 40 l00 Input Supply voltage Vcc 45 5.5 Volts28 Tolal Oulpul Supply Vollage lcCr-VEe 15 0 9 Negalive Outpul Supply vollage IVE- VEE) 15 Posilive Oulpul Supply vollage (VCC2-VE 30-(- VEE Collector volta Vc VEE +6 6章208253PDF用) Page 214 01.5.24, 4: 35 PM Adhe P ageM aker 6.0upPC HCPL31 6J Electrical Specifications Dc Unless otherwise noted, all typical values at TA= 25C. Ve c1=5 V, and vi x -VEE:=30V, VE- VRK=0V: all MininuIn/MaximuIn specifications are aL Recommended Operaling Condilions Parameter Symbol Min. Typ. Max. Units Test Conditions Fig. Note Logic low input 0.8 Voltages RESETI Logic High Input 2.0 Voltages RESETH Logic Low input IN+Lt IN-L 0.5 V=0.4V Currents REsEtS FAULT Logic Low faull 5.0 VEAULT =0.4 v Oulput Current FAULT Logic High All,TH 40 LA V Output current High Level Output 0.5 A VOUT= Vcc2-4V3.8.7 Current OUT= Vcc2-15V32 Low Level Output 0.5 2.3 VOUT=VEE+2.5v49.7 Current 2.0 VOUT VEE +15 V Low Level output 90 nA VOUT- VEE=14V534 8 Current during Fault Condition High Level Output v-35ve-25Vc-1.5 Iour=-100mA6,8,9,10, Voltage Ve-2.9Ve-20Vc-1.2 IoUr=-650μA 11 Low Level oulpul V 0.17 0.5 IOUT= 100 InA 7,9,26 Voltage 36 High Level Input 17 22 nA IN+ Vcl=5.5V,10 Supply current VⅣ=0V 37 Low Level Input 6 11 38 Supply Current Vccl=5.5V Output Supply CC2 2.5 VOUT open 11,12,11 Current 39,40 Low Level Collector Ic 0.3 1 Current High Level Collector Current l.8 IoUr=-650μA15,57 VE Low Level Supply 0.4 Current VE High Level Supply 0.5 -0.14 Current 40 g cap Icr 0.13 -0.25 0.33 0-6V Charging Curren 0.18 -0.25 6V 4112 TA=25C-100°C Blanking Capacitor DSCHG 50 VDESAT =7 V 42 Current UVLO Threshold UVLO l1.6 12.3 13.5 VouT >5V 439,11, 1 3 l1.1 12.4 Vour<5 V 9.11 14 0.4 l.2 DESAT Threshold 6.5 7.0 6-215 6章208253PDF用) Page 215 01.5.24, 4: 35 PM Adobe P ageM aker 6.0JPPC HCPL31 6J Switching Specifications(Ac) Unless otherwise noted, all typical values at TA =25C, Ve c1=5v, and vI -V-H=30V. VE-VKE=0 V: all Minimum/Maximum specifications are at Recommended Operating Conclitions Parameter ymbol Min. Typ. Max. Units Test Conditions Fig. Note VIN to High Level Output PLH 0.10030050usRg=109 17,18,19.15 PropagaTion Delay Time g= l0 nF 20,21,22 VIn to Low Level output 0.100320.50 f= 10 kHz 45,54, Propagation Delay Time Duty cycle 50% Pulse width Distortion PWD 0300.020.30 16,17 Propagation Delay Difference(tPHL-tPLH) -0.35 0.35 1718 Between Any Two Parts PDD 10% Lo 90% Rise Time tr 0.1 45 90 to 10% Fall Time tr 0.1 DESAT Sense to 90% ouT tDESAT(90%) 0.30.5 Rg=10 Q2 235619 Delay Cg=10 nH DESAT Sense to I0%O VouT DESAt(lo% 2.03.0 VCC2-VEE=30 V 24,28 Delay DESAT Sense lo Low level DESAT(FAOLT) 1.85 25,47 20 FAULT Signal Delay DESAT Sense to DESAT Low tDESAT(LoW 0.25 Propagation Delay reset to High Level Fault tRESETIFAULT)37 20 26,27.22 Signal Delay RESET Signal Pulse Width PWRESET O.1 UVLO tO VOUT High Delay 4.0 1.0ms 13 ramp uvlo to Vour low delay tULO OFF 6.0 14 Output high Level common I CMH I 15 30 kV/usTA=25°C 50.51 23 Mode Transient Immunity VCM=1500V Vcc =30 V Output Low Level common I CML I 1530 TA=25°C, 24 Mode Transient Immunity 1500V, Vc;9=30V 6-216 6章208253PDF用) Page 216 01.5.24, 4: 35 PM Adhe P ageM aker 6.0upPC HCPL31 6J Notes 1. In accordance with ULI577. each optocoupler is 11. Once VOur of the HCPL-316J is allowed to go high proof tested by applying an insulation test voltage UVCC2-VE>VUVLo, the desat detection feature of 24200 Vrms for l second (leakage detection current the HCPL-316J will be the primary source of IGBT limit, IIo<5 HA). This test is performed before the protection. UVLO is needed to ensure DESat is 100% production test for partial discharge(method functional. Once vUvLo+ >11.6. DESAT will shown in VDE 0884 Insulation Characteristic remain functional until Vuvlo.< 12 4V. Thus the able, if applicable deSat detection and uvlo features of the hcPl 2. The: Input-Output Momentary Withstand Voltage 316 work in conjunction to ensure constant IGBT is a dielectric voltage rating that should not be interpreted as an input-output continuous voltage 12. See the Blanking Time Control section in the raling. For the continuous vollage raling refer to applications notes at the end of this data sheet for your equipment level safety specification or further details VDEO884 InsulaTion Characterislics Table 13. This is the“ Increasing”(ie.turn-onor“ positIve 3. Device considered a two terminal device: pins 1-8 going " direction) of VCc2-VE shorted together and pins 9-16 shorted together. 14. This is the decreasing"(i.e turn-off or "negative 4. In order to achieve the absolute maximum power going"direction) of Vcc2-V dissipation specified, pins 4, 9, and 10 require 15. This load condition approximates the gate load of ground plane connections and may require airflow a 1200 V/75A IGBT See the Thermal Model section in the application 16. Pulse Width Distortion (PWD) is defined as I tHHi notes at the end of this data sheet for details on Lru I for any given unit how to estimate junction temperature and power 17. As measured from VIN+, VIN- to Vou dissipation. In most cases the absolute maximum 18. The difference between trIL and truI between any output IC junction temperature is the limiting two HCPL-316J parts under the same test factor. The actual power dissipaTion achievable will conditions depend on the application environment (PCB 19. Supply Voltage Dependent. Layout, air flow, part placement, etc. ) See the 20. This is the amount of time from when the: DESAT Recommended PCB Layout section in th threshold is exceeded, until the FaUlt output goes application notes for layout considerations. Output low IC power dissipation is derated linearly at 10 mw/ 21. This is the amount of time the dESat threshold ° c above90°C. Input IC power dissipation does must be exceeded before Vout begins to go low not require derating and the FAULT oulpul Lo go lor 5. Maximum pulse width=10 us, maximum duty cycle 22. This is the amount of time from when RESET is =0.2%. This value is intended to allow for compo asserted low, until FAULT output goes high. The nent tolerances for designs with lo peak minimum minimum specification of 3 us is the guaranteed 2.0 A. See Applicalions section for addilional minimum FAULT signal pulse width when the details on I H peak. Derate linearly from 3.0 A at HCPL-316 is configured for Auto-Reset. See the +25°Cto2.5Aat+100°C. This compensates for Auto-Reset section in the applications notes at the increased IoPEAk due to changes in VoL over end of this data sheet for further detai temperature 23. Common mode transient immunity in the high state 6. This supply is optional. Required only when negative the maximum tolerable dVcm/dt of the common gate drive is implemented mode pulse, ve M, to assure that the output will 7. Maximum pulse width= 50 us, maximum duty cycle renna in he high slate (i. e, Vo>15 V or FAULT 0.5%. >2V]. A l00 pF and a 3K 2 pull-up resistor is 8. See the Slow IGBT Gate Discharge During Fault needled in fault detection mode Condition section in the applications notes at the 24. Common mode transient immunity in the low state end of this dala sheet or lurther delails is the maximum tolerable vCm/dt of the common 9. 15 V is the recommended minimum operating mode pulse, Vcm, to assure that the output will positive supply voltage (Vcc2-VE) to ensure remain in a low state i.e., Vo< 1. 0V or FaUlt< adequate margin in excess of the maximum VuvLO+ 0.8V. threshold of 13.5V. For High Level Output Voltage 25. Does not include LED2 current during fault or testing VOH is measured with a dc load current blanking capacitor discharge current. When driving capacitive loads, VoH will approach 26. To clamp the output voltage at Vcc-3VBE, a pull Vcc as loH apl hes zero units bely 10. Maximum pulse width= 1.0 ms, maximum duty recommended to sink a static current of 650 HA cle= 20% while Che oulpul is high. See the Oulpul Pull-Down Resistor section in the application notes at the end of this data sheet if an output pull-cown resistor is not used 6章208253PDF用) Page 217 01.5.24, 4: 35 PM Adobe P ageM aker 6.0JPPC

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