DFT Compiler Scan User Guide Version E-2010.12-SP2

文件名称: DFT Compiler Scan User Guide Version E-2010.12-SP2, March 2011.pdf

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详细说明：DFT Compiler Scan User Guide , for those who want to study DFT/Scan design.Contents Whats New in This release XX About this guide XX Customer Support 1■口 XXII . Key Design-for-Test Flows and Methodologies Design-for-Test Flows in the Logical Domain 1-2 Unmapped Design Flow 1-2 Synthesizing Your design 1-4 ■■■■■■ Postprocessing Your Design 1-5 Building Scan Chains 1-6 Mapped Design Flow Reading In Your Design 1-10 Performing Scan Replacement and Building Scan Chains 1-11 Mapped Designs With Existing Scan Flow 1-13 Reading In Your Design 1-15 Checking Test Design Rules 1-16 Designing Block by Block. 1-17 Controlling Scan Replacement During Scan Insertion 1-17 Hierarchical Scan Synthesis Flow 1-18 Introduction to test models 1-19 Linking Test Models to Library Cells 1-23 Checking If a Library Contains CTL Models 1-23 Scan Assembly Using Test Models 1-23 Saving Test Models for Subdesigns 1-24 Using Test Models 1-25 III DFT Compiler Scan User Guide Version E-2010.12-SP2 Reading designs Into TetraMAX 1-27 Managing Test Models 1-27 Top-Level Integration ■■■ 1-30 Hierarchical ScanEnable Integration.......... 1-32 DFT Flows in Design Compiler Topographical Mode 1-33 Supported dft Features 1-34 DFT Insertion Flow in Design Compiler Topographical Mode 1-35 Running DFT Insertion in Design Compiler Topographical Mode 1-35 Error messages 1-35 Hierarchical Support in Design Compiler Topographical Mode 1-36 Top-Level Design Stitching Flow 1-36 Bottom-Up/Hierarchical Flow With Test Models 1-38 Scan Insertion Methodologies 1-42 Bottom-Up Scan Insertion 1-42 Top-Down Scan Insertion 1-44 DFT Compiler Default Scan Synthesis Approach 1-45 Scan Replacement 1-46 Scan Element allocation 1-46 Test signals 1-46 Pad cells 1-47 Area and Timing optimization 1-47 Getting the Best Results With Scan design 1-48 DFT Compiler and Power Compiler Interoperability 1-49 Improving Testability in Clock Gating 1-49 Inserting Control Points in Control Clock Gating 1-50 Scan enable Versus Test mode 1-51 Inserting Observation Points to Control Clock Gating 1-53 Choosing a Depth for Observability Logic 1-55 Power Compiler/DFT Compiler Interoperability Flows 1-55 Using test_mode With Power Compiler 1-55 Connecting Test Pins to Clock-Gating Cells Using insert_dIf Using scan Enables with power compiler 1-56 1-59 Design Requirements 1-60 Hookup Testport Connections 1-61 Design Rule Checking Changes 1-61 Contents DFT Compiler Scan User Guide Version E-2010.12-SP2 Specifying a Particular Signal as Test Pin When Automatically Connecting Test Ports to Clock-Gating Cells 1-62 Limitations 1-64 2. Running RTL Test Design Rule Checking Understanding the Flow ■ 2-2 Specifying Setup Variables................ 2-3 Generating a Test Protocol 2-3 Defining a test Protocol 2-3 Reading in an Initialization protocol in STIL Format 2-4 Setting the Scan Style Design EXamples. 2-8 Test Protocol Example 1 2-8 Test Protocol Example 2 2-9 Running RTL Test DRC 2-12 Understanding the Violations 2-13 Violations that prevent scan Insertion 2-13 Uncontrollable Clocks 2-13 Latches Enabled at Beginning of Clock Cycle ............ 2-14 Asynchronous Control Pins in Active state 2-14 Violations That Prevent Data Capture 2-15 Clock Used As data 2-15 Black Box Feeds Into Clock or Asynchronous Control 1 2-16 Source Register Launch Before Destination Register Capture 2-16 Registered Clock-Gating Circuitry 2-17 Three-State Contention 2-18 Clock Feeding Multiple Register Inputs 2-19 Violations That Reduce Fault Coverage 2-19 Combinational Feedback Loops 2-19 Clocks That Interact With Register Input 2-20 Multiple Clocks That Feed Into Latches and flip-Flops........ 2-21 Black Boxes 2-22 Limitations 2-23 3. Running Test DRC Debugger Starting and Exiting the Graphical User Interface 3-2 Contents DFT Compiler Scan User Guide Version E-2010.12-SP2 EXploring the Graphical User Interface 3-2 ogic Hierarchy View 3-4 Console window ■口■ 3-4 Command line 3-4 Viewing Man Pages Menus 3-5 Checking scan Test design rules 35 Examining drc violations -6 Viewing Test Protocols 3-6 Viewing Design Violations Examining DRC Violations 3-7 Inspecting DRC Violations 3-8 Inspecting Static DRC Violations 3-8 Viewing a violation 重重 39 Viewing multiple violations 3-12 Viewing CTL Models 3-13 Inspecting Dynamic DRC Violations 3-15 Commands specific to the DFT GUI 3-17 gui_inspect_ violations 3-17 gui_wave_add_signal ■着着 3-18 gui_violation_schematic_add_objects 3-19 4. Performing Scan Replacement Scan Replacement Flow 4-3 Preparing for Scan Replacement Selecting a Scan Replacement Strategy 4-4 dentifying Barriers to Scan Replacement 4-5 Technology Library Does Not Contain Appropriate Scan Cells 4-6 Support for Different Types of Sequential Cells and violations 4-7 Attributes That Prevent Scan Replacement 4-8 Invalid Clock Nets 4-9 Invalid Asynchronous pins ■1■ 4-11 Preventing Scan Replacement Specifying a Scan Style 4-12 Types of Scan Styles 4-12 Multiplexed Flip-Flop Scan Style 4-13 Clocked Scan Style 4-13 Contents DFT Compiler Scan User Guide Version E-2010.12-SP2 LSSD Scan Style 4-13 Scan Style Considerations 4-14 Setting the Scan Style 4-15 Verifying Scan Equivalents in the Technology Library 4-15 Checking the Technology library for Scan Cells 4-16 Checking for Scan equivalents 4-17 Scan Cell Replacement Strategies 4-17 Specifying Scan Cell ■■ 4-18 Restricting the List of Available Scan Cells 4-18 Sample Scan Cell Replacement Strategies 4-18 Mapping Sequential Gates in Scan Replacement 4-19 Multibit components 4-20 What Are Multibit Components? 4-21 How DF T Compiler Assimilates Multibit Components 4-21 Controlling Multibit Test Synthesis 4-22 Performing Multibit Component Scan Replacement 4-22 Disabling Multibit Component Support 4-22 Test-Ready Compilation 4-23 What Is Test-Ready compile? 4-23 The Test-Ready Compile Flow 4-24 Preparing for Test-Ready Compile 4-25 Performing Test-Ready Compile in the Logical Domain 4-26 Controlling Test-Ready Compile 4-26 Comparing Default Compile and Test-Ready Compile 4-27 Complex Compile strategies 4-30 alidating your netlist 4-31 Running the link Command 4-31 Running the check_design Command 4-32 Performing Constraint-Optimized Scan Insertion 4-32 Supported scan states 4-32 Locating Scan Equivalents 4-33 Preparing for Constraint-Optimized Scan Insertion........... 4-35 Scan Insertion 4-35 Specification Phase 4-37 Preview 4-39 Synthesis 4-39 Contents DFT Compiler Scan User Guide Version E-2010.12-SP2 5. Pre-Scan Test Design Rule checking Test drc basics -2 Test DRC Flow 5-2 Preparing Your Design Creating the Test Protocol 5-4 Assigning a Known Logic State -5 Performing Test Design Rule Checking 5-5 Analyzing and Debugging Violations 5-5 Summary of violations 5-6 Enhanced Reporting Capability Test Design Rule Checking messages 58 Test Design Rule Checking Message Generation 5-9 Understanding Test Design Rule Checking Messages Effects of violations on Scan Replacement 5-9 Viewing the Sequential Cell Summary 5-10 Classifying Sequential Cells 5-11 Sequential Cells With violations 5-11 Cells With scan shift violations 5-11 Black-Box Cells 5-12 Constant Value Cells 5-12 Sequential Cells Without violations 5-12 Checking for Modeling violations 5-12 Black-Box Cells 5-13 Correcting Black Box Cells 5-13 supported cells Generic Cells 5-16 Scan Cell Equivalents 5-16 Scan Cell Equivalents and the dont touch Attribute 5-17 Latches 5-17 Nonscan latches 5-18 Setting Timing Attributes 5-18 Protocols for Common Design Timing Requirements 5-18 Strobe-Before-Clock Protocol 5-19 Strobe-After-Clock Protoco 5-19 Setting Timing Attributes 5-19 test_default_period Attribute 5-20 test_default_delay variable __· 5-20 test_default_bidi_delay Attribute 5-20 Contents DFT Compiler Scan User Guide Version E-2010.12-SP2 test default strobe variable 5-22 test default strobe width variable 5-22 The Effect of Timing Attributes on Vector Formatting 5-24 Creating Test Protocols 5-24 Design Characteristics for Test Protocols 5-25 scan_style Attribute 5-25 signal_type Attributes 5-25 Clock Ports 5-25 Asynchronous Control Ports 5-26 Bidirectional Ports 5-26 STIL Test Protocol File Syntax.…...,,,…… 5-26 Defining the test_setup Macro 5-27 Defining Basic Signal Timing 5-27 Defining the load_unload Procedure..∴.∴ 5-29 Defining the Shift Procedure 5-29 Defining an Initialization Protocol 530 Scan Shift and Parallel cycles 5-32 Multiplexed Flip-Flop scan Style 5-32 Clocked-Scan Scan Style .......... 5-33 LSSD Scan Style 5-33 EXamining a Test Protocol File∴.….…… 5-34 Updating a protocol in a Scan Chain Inference flow 5-36 Masking DRC Violations 5-36 Setting the Severity of DRC violations 5-37 Resetting the Severity of DRc Violations 38 Reporting the Severity of DRC Violations 5-39 6. Architecting Your Test Design Configuring Your DFT Architecture 6-3 Defining your scan architecture 6-3 Setting Design Constraints........ 6-4 Defining Constant Input Ports During Scan 6-4 Specifying Test Ports Specifying Individual Scan Paths 65 Previewing Your Scan Design 66 Using preview_dft Versus report_scan_path 6-7 Architecting Scan Chains 1重1 1重 6-7 Specifying a Scan Chain for the Current Design 68 Contents DFT Compiler Scan User Guide Version E-2010.12-SP2 Controlling the Scan Chain Length 1 6-8 Specifying Limits for Individual scan Chain Length 6-8 Specifying the Global Scan Chain Exact Length 6-9 Specifying the Global Scan Chain Length Limit 6-9 Determining the scan chain count 6-10 Balancing Scan Chains 6-10 Multiple Clock Domains 6-11 Multibit Components and Scan Chains 6-13 Controlling the Routing Order 6-15 Routing Scan Chains and Global Signals 6-16 Rerouting Scan Chains 6-16 Stitching Scan Chains Without optimization 6-17 Specifying a Stitch-Only Design 6-17 Mapping the Replacement of Nonscan Cells to Scan Cells 6-18 Conditions Under Which Scan Cells Are Excluded or nonscan cells become scan cells 6-20 Using existing Subdesign Scan Chains 6-21 Uniquifying Your Design ■日着1 6-23 Reporting Scan Path Information on the Current Design 6-24 Architecting Scan Signals 6-24 Specifying Scan Signals for the Current Design 6-26 Selecting Test Ports 6-30 Sharing Scan-In Pins With Multiple Scan Chains 6-30 Sharing a scan Input With a functional port 6-31 Sharing a Scan Output With a Functional Port 6-31 Associating Scan Enable Ports With Multiple Scan Chains 6-33 Defining a Dedicated Scan Enable Signal for Connecting Only to Scan Cells 6-33 Connecting the Scan Enable Signal in Hierarchical Flows 6-36 Using Dedicated Scan Output Ports 6-38 Suppressing Replacement of Sequential Cell 6-38 In Logical Scan Synthesis 6-39 Changing the Scan State of a Design 6-39 Removing Scan Specifications∴...…….… 6-40 Keeping Specifications Consistent 6-41 Synthesizing Three-State Disabling Logic 6-41 Configuring Three-State Buses 6-44 Configuring External Three-State Buses 6-44 Configuring Internal Three-State Buses 6-45 Contents

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