DDR_PHY_Interface_Specification_v5_0.pdfDFI 5.0 sp

文件名称: DDR_PHY_Interface_Specification_v5_0.pdf

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详细说明：DFI 5.0 spec，DDR PHY 5.0规格，上传备用 The DDR PHY Interface (DFI) is an interface protocol that defines the signals, timing parameters and programmable parameters required to transfer command information and data across the DFI and between the MC and the PHY.Nov 2013 Incorporated review corrections 21 Mar 2014 Incorporated committee comments, corrected erroneous cross references, fine-tuned formatting, fine-tuned typographical items 4.0 04 Aug 2017 Merged DFI 4.0 Spec Addendum to DFI 3. 1. Added support for LPDDR4, DB training, per slice read leveling, DFI read/write chip select, write DQ training, PhY master interface, frequency indicator, DFI disconnect protocol, DFI data bit disabling, slice parameter, geardown mode, DFI feature and matrix topology matrix, 3D stack support and inactive CS support. Also modified CA training, write leveling strobe and changed thc dFI training to bc optional. Enhanced dFi read data eve training sequence, update interface for self-refresh exit 20 Jul 20 17 Incorporated rcvicw changes from 4.0 Addendum mcrgc oprietary Notice No part of this document may be copied or reproduced in any form or by any means without prior written consent of Cadence Cadence makes no warranties with respect to this documentation and disclaims any implied warranties of merchantability or fitness for a particular purpose. Information in this document is subject to change without notice Cadence assumes no responsibility for any errors that may appear in this document Except as may be explicitly set forth in such agreement, Cadence does not make, and expressly disclaims, any representations or warranties as to the completeness, accuracy, or usefulness of the information contained in this Cadence assume any liability for damages or costs of any kind that may result from use of such information oes document. Cadence does not warrant that use of such information will not infringe any third party rights, nor does C Copyright 2017 Cadence Design Systems, Inc. All rights reserved worldwide. Portions of this material are C JEDEC Solid State Technology Association. All rights reserved. Reprinted with permission RESTRICTED RIGHTS LEGEND Use, duplication, or disclosure by the Government is subject to restrictions as set forth in subparagraphs(c)(1)(ii)of the Rights in Technical data and Computer Software clause at DFarS 252.227-7013 Destination control statement All technical data contained in this product is subject to the export control laws of the United States of America Disclosure to nationals of other countries contrary to United States law is prohibited. It is the reader's responsibility to determine the applicable regulations and to comply with them Trade Cadence and the Cadence logo are registered trademarks of Cadence Design Systems, Inc All other products or brand names mentioned are trademarks or registered trademarks of their respective holders End User License Agreement2 1. Subject to the provisions of Clauses 2, 3, 4, 5 and 6, Cadence hereby grants to licensee("Licensee)a perpetual nonexclusive, nontransfcrablc, royalty frcc, worldwide copyright license to usc and copy thc DFI(DDR PHY Intcrfacc) specification(the"DFI Specification )for the purpose of developing, having developed, manufacturing, having manufactured, offering to sell, selling, supplying or otherwise distributing products which comply with the DFI specificatio 2.THE DFI SPECIFICATION IS PROVIDED"AS IS" WITH NO WARRANTIES EXPRESS IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO ANY WARRANTY OF SATISFACTORY QUALITY MERCHANTABILITY. NONINFRINGEMENT OR FITNESS FOR A PARTICULAR PURPOSE 3. No license, express, implied or otherwise, is granted to Licensee, under the provisions of Clause l, to use Cadence's or any other person or entity participating in the development of the dFI Specification listed herein(individually DDR PHY Interface. Version 5.0 3°f160 Aprl27,2018 Copyright 1995-2018 Cadence Design Systems, Inc Participant, collectively"Participants")trade name, or trademarks in connection with the dFI Specification or any products based thereon. Nothing in Clause l shall be construed as authority for Licensee to make any representations on behalf of Cadence or the other Participants in respect of the DFI Specification 4. NOTWITHSTANDING ANYTHING ELSE WILL CADENCES TOTAL AGGREGATE LIABILITY FOR ANY CLAIM. SUIT. PROCEEDING OR OTHERWISE RELATING IN ANY WAY TO THE DFI SPECIFICATION EXCEED S1.00USD 5.NOTWITHSTANDING ANY THING ELSE WILL ANY PARTICIPANTS TOTAL AGGREGATE LIABILITY FOR ANY CLAIM. SUIT. PROCEEDING OR OTHERWISE RELATING IN ANY WAY TO THE DFI SPECIFICATION EXCEED S1.00USD 6. Licensee agrees that Cadence and the Participants may use, copy, modify, reproduce and distribute any written comments or suggestions("Communications")provided regarding the dFI Specification by Licensee and that Licensee will not claim any proprietary rights in the DFI Specification, or implementations thereof by any Participant or third party, as a result of the use of the Communications in developing or changing the DFI Specification. Cadence and the participants will have no confidentiality obligations with respect to the Communications and licensee will not include any confidential information of Licensee or any third party in any Communications Participants AMd ARM Broadcom Cadence Intel Samsung ST Synopsys Uniquify 4of160 DDR PHY Interface. Version 5.0 Copyright 1995-2018 Apr27,2018 Cadence Design Systems, Inc Contents 1.0 Overview 15 2.0 Architecture 16 2.1 Clocking 16 2.2 Optional Protocols........... 19 2.3 DFI Feature Requirements 2.3.1 Global Features 20 2.3.2 Memory Topology-Specific Features 20 2.3. 3 DFI Signals 22 2. 4 Definition of a slice 31 3.0 Interface Signal Groups 33 Command interface.,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,33 3. 1. 1 Mapping the Ca Bus to the dfi address Bus 3.1.2 Clock Disabling 34 3.1.3 Frequency Ratio Systems 34 3.1.4 CRC and CA Parity 34 3.2 Write Data Interface 39 3.2.1 Write Data Mask/ Write Dbi 39 3.2.2 Write Data Chip select 39 3.2.3 Write Data CrC 39 3.2.4 Frequency Ratio 40 3.2.5 Write Data Signals and Parameters 40 3.3 Read data interface。,,,,,,,,,。,,,, 43 33.1 Read DBl 43 3.3.2 Read Data Chip select 43 3. 3.3 Read Data Valid 43 3.3.4 Frequency Ratio 44 3.3.5 Read Data Signals and Parameters DDR PHY Interface. Version 5.0 5°f160 Aprl27,2018 Copyright 1995-2018 Cadence Design Systems, Inc 3. 4 Update Interface 47 3.5 Status Interface。。。,,,,。,。,,,,,, 51 3.5.1 Initializatio 5 3.5.2 Reduced data buses 3.5.3 Frequency ratio 51 3. 5.4 Frequency Change 52 3.5.5 Frequency Indicator..∴..,…,… 52 3.5.6 Status Interface Signals and Parameters 3.6 Low Power Control interface 56 3.7 Error Interface 62 3. 8 PHY Master interface....,...... ·····.···········.··············· 63 3.8.1 Inactive Chip Selects 63 3.8.2 PHY Master Interface Signals and Parameters 3.9 Disconnect protocol 67 3.10 2N Mode Interface 69 3. 11 MC to phY Message interface 3.12 WCK Control interface。,。。,,,。。,。,,,,。,, 71 3.13 Channels for multi-Channel memories 73 4.0 Functional Use..,,。。。,,,,, 75 4.1 Initialization..。,,,,,。,,。,,,,,,, ·番·自自。。 75 4.2 PHY Independent Training Boot Sequence 76 4.2.1 Refresh Requirements 77 4.2.2 Boot into self-Refresh 4.3 Command Interface Signals ................................................77 4.4 DFI Clock Disabling 4.53 DS Stack Support.………………… 8 4.5.1 3DS Addressing with dfi cid and dfi cs for DDR3 81 4.5.2 3DS Addressing with dfi cid and dfi cs for DDR4 81 4.6 Data bus inversion 82 4.7 Write transactions,,,,,,,。,,,,。,,,,。。,,。,,, 83 6of160 DDR PHY Interface. Version 5.0 Copyright 1995-2018 Apr27,2018 Cadence Design Systems, Inc 4.7.1 Write Transaction Sequence 83 4.7.2 DbI- Write 4.7.3 Cyclic Redundancy Check 91 4.7.3. 1 MC CRC Support (phycrc mode=0) 91 4.7.3. 2 PHY CRC Support(phycrc mode= 1) 94 4.7.3. 3 Burst Chop 4 with PHY CRC Support 95 4. 8 Read transactions 。。。。看·.·鲁鲁。。。。鲁鲁 97 4.8.1 Read Transaction Sequence 98 4.8.2 DBI-Read 105 4.8.2.1 MC DBI Support (phydbi mode=0) 105 4.8.2. 2 PHY DBI Support(phydbi mode= 1) 105 4.9 Update..... 105 4.9.1 MC-Initiated Update · .105 4.9.2 PHY-Initiated Update 106 4.9.3 DFI Idle 107 4.10 Frequency Ratios Across the DFI.…………………… 108 4.10.1 Frequency Ratio Clock Definition .·· 109 4.10.2 Interface Signals with Frequency Ratio Systems 109 4.10.3 Write Data Interface in Frequency Ratio Systcms 113 4.10.4 Read Data Interface in Frequency Ratio Systems 垂.·· 116 4. 10.4.1 DFI Read data rotation 123 4.10.4.2 Read data resynchronization 127 4.11 Frequency Change 127 4.11. 1 Frequency Change Protocol -Acknowledged 128 4.11.2 Frequency Change Rcqucst Protocol-Not Acknow ledged .130 4.12 CA Parity Signaling and Ca Parity, CRC Errors 130 4. 12.1 CA Parity Timing 131 4.12.2 CA Parity and CrC Errors 131 4. 12.3 CA Parity and CRC Errors in Frequency Ratio Systems 31 4.13 Low Power Control Handshaking.,...... 133 DDR PHY Interface. Version 5.0 70f160 Aprl27,2018 Copyright 1995-2018 Cadence Design Systems, Inc 414 Error signaling∴………∴∴∴ 137 4.15 PHY Control of the dfi bus,,,,。,,,,。,,,,,。,,,,,,,,,,。,,,,,,,。,,,,,,,。,,,138 4.16 DFI Disconnect protocol 140 4.16.1 Update Interface 4.16.2 PHY Master Interface 141 4.17 Use of the 2N Mode 142 4. 18 Use of the mc to phy message interface 鲁鲁.鲁鲁着鲁D。。。。。。看·。。。。鲁鲁 145 4.18.1 Timing Diagram l46 4.18.2 PHY Messages 46 4.18.3 Information Data Signal 147 4.19 Use of the WcK Control Interface..................... 147 4.20 Channel Operation for Multi-Channel memories 149 4.20.1 Independent Operation ··· · · 149 4.20.2 Combined operation·…… l50 4.20.2. 1 Update Interface 151 4.20.2.2 Status Inter face .151 4.20.2. 3 Low Power Interface 151 20.3 Multi-Configuration Support 151 4.21 DFIInteractions 152 5.0 Signal Timing. 155 6.0 Glossary∴… l58 8of160 DDR PHY Interface. Version 5.0 Copyright 1995-2018 Apr27,2018 Cadence de Systems, I List of tables TABLE 1. Interface Groups 15 TABLE 2. Signals by clock Domain 17 TABLE 3. Features by Memory Topology ...20 TABLE 4. DFI Signal requirements ,,,,,,,,,,24 TABLE 5. DFI Data Slice Definition Programmable Parameters table 6. Bit Definitions of the dfi address bus for lpddr2 and lpddr3 TabLE 7. Bit Definitions of the dfi address bus for LPddr5 33 tabLe 8. Command Interface signals .....34 TABLE 9. Command Interface Timing Parameters 37 TABLE 10. Command Interface Programmable parameters ···章4 38 TABLE 11. Write Data Interface Signals 0 TABLE 12. Write Data Interface Timing Parameters ,,,,,,,,,,,,,,,,,,,,,,,,,41 TABLE 13. Write Data Interface Programmable Parameters TABLE 14. Read Data Interface Signals .44 TABLE 15. Read Data Interface Timing Parameters D·垂 46 TABLE 16. Read Data Interface Programmable Parameter 46 TABLE 17. Update Interface Signals 48 TABLE 18. Update Interface Timing Parameters 50 TABLE 19. Status Interface Signals 53 TABLE 20. Status Interface Timing Parameters TABLE 21. Status Interface Programmable Parameter 56 TABLE 22. Low Power Control Interface Signals 57 TABLE 23. Low Powcr Control Intcrfacc Timing Paramctcrs TABLE 24. Low Power Control interface programmable parameters 61 TABLE 25. Error Interface Signals ,,,,,,,,,,,,,,,,,,,,,,,,62 TABLE 26. Error Interface Timing parameter 63 TABLE 27. PHY Master Interface Signals .,,,,,..64 DDR PHY Interface. Version 5.0 9°f160 Aprl27,2018 Copyright 1995-2018 Cadence Design Systems, Inc TABLE 28. PHY Master Interface Timing Paramctcrs 66 TABLE 29. PHY Master Interface Programmable Parameter 67 TABLE 30. MC/ PHY Handshaking Interfaces and Signal 68 TABLE 31. Disconnect Protocol Signal 68 TABLE 32. Disconnect Protocol Timing Parameters 68 TABLE 33. 2N Mode Interface Signal 70 TABLE 34. 2N Modclntcrfacc Timing Parameter ....,70 TABLE 35. 2N Mode Programmable parameters 70 TABLE 36. MC to PHY Message Interface Signals 垂·音 71 TABLE 37. MC to Phy Message Interface Timing Parameters 71 table 38. WCK Control interface signals 72 TABLE 39. WCK Control Interface Timing Parameters 72 TABLE 40. DFI Data Channel Programmable Paramctcrs TABLE 41. DDR3 Contiguration with 8 Logical and 1 Physical Rant ..,74 .81 TABLE 42. DDR4 Configuration with Logical and 2 Physical ranks 82 TABLE 43. Systems Requiring CRC Support 91 TABLE 44. dfi alert n Signal With Matched and Frequency Ratio Systems ....... 132 TABLE 45. Error Codes 138 TABLE 46. Controller Message Codes ··看 146 TABLE 47. Data Signal codes ,,,,,,147 TabLE 48. DFi Interactions 152 TABLE 49. Signal Group divisions ..156 TABLE 50. Glossary of Terms ......158 10of160 DDR PHY Interface. Version 5.0 Copyright 1995-2018 Apr27,2018 Cadence Design Systems, Inc

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