JESD250B.pdfJEDEC GDDR6 spec,上传备用 This document de

文件名称: JESD250B.pdf

所属分类: 其它

开发工具:

文件大小: 2mb

下载次数: 0

上传时间: 2019-09-13

提供者: u0121*****

下载 (2mb)

不能下载？报告错误

详细说明：JEDEC GDDR6 spec,上传备用 This document defines the Graphics Double Data Rate 6 (GDDR6) Synchronous Graphics Random Access Memory (SGRAM) specification, including features, functionality, package, and pin assignments.PLEASE DONT VIOLATE THE LAWE This document is copyrighted by the JEDEC Solid State Technology Association and may not be reproduced without permission Organizations may obtain permission to reproduce a limited number of copies through entering into a license agreement. For information, contact JEDEC Solid State Technology Association 3103 North 10th street, suite 240S Arlington, Virginia 22201 or call(703)907-7559 JEDEC Standard No 250B Contents 1 SCOPE 2 GDDR6 SGRAM STANDARD OVERVIEW 2.1 FEATURES 2.2 FUNCTIONAL DESCRIPTION 2.3 DEFINITION OF SIGNAL STATE TE 2.4 DEFINITION OF CLOCKING TERMINOLOGY 2.5 CLOCKING 2.6 STATE DIAGRAM 122344580 3 INITIALIZATION∴ 3.1 POWER-UP SEQUENCE ,..10 3.2 INITIALIZATION WITH STABLE POWER 3.3 VENDOR D 4 ADDRESS 17 4.1 COMMAND and ADDRESSING 17 4.2 COMMAND ADDRESS BUS INVERSION (CABD) 4 3 BANK GROUPS 5 TRAINING 21 5.1 INTERFACE TRAINING SEQUENCE .21 5.2 COMMAND ADDRESS TRAINING 5.3 WCK2CK ' TRAINING 5.4 READ TRAINING 5.5 WRITE TRAINING 6 MODE REGISTERS 6. 1 MODE REGISTERO(MRO) ...44 6.2 MODE REGISTER 1(MR1)................ 6.3 MODE REGISTER 2(MR2) 6.4 MODE REGISTER 3(MR3) 6.5 MODE REGISTER 4(MR4) 6.6 MODE REGISTER 5 (MRS 6.7 MODE REGISTER 6(MR6)& MODE REgiSter 9(MR9) 6.8 MODE REGISTER 7(MR7) 6.9 MODE REGISTER 8 (MR8) 6.11 MODE REGISTER 11(MRI1 6.12 MODE REGISTER 12(MR12 6.14 MODE REGISTER 14(MR14 6.15 MODE REGISTER 15 (MR15 7 OPERATION∴ 7.1 COMMANDS 74 7.2 COMMAND, ADDRESS and WRITE DATA INPUT TIMINGS 76 7.3 NOOPERATION(NOP) ...76 7.4 MODE REGISTER SET 7.5 ROW ACTIVATION 7.6 BANK RESTRICTIONS 7.7WRTE(wOM).…,…,, 7.8 WRITE DATA MASK (DM) 7.9 MASKED WRITE DATA TIMING CONSTRAINTS 95 710 READ 7.11 DQ PREAMBLE 7.12 RDQS MODE..… ·· 105 7. 13 READ and WRITE DATA BUS INVERSION (DBI) 7.14 ERROR DETECTION CODE (EDC) 108 7.15 PRECHARGE 7.16 AUTO PRECHARGE · 113 7. 17 REFRESH and PER-BANK/PER-2-BANK REFRESH 7. 1 8 SELF REFRESH 7.19 PARTIAL ARRAY SELF REFRESH (PASR) 7.20 HIBERNATE SELF REFRESH 7.21 HIBERNATE SELF REFRESH WITH VDDQ OFF 7.22 POWER-DOWN 128 JEDEC Standard No 250B 7.23 COMMAND TRUTH TABLES 7.24 CLOCK FREQUENCY CHANGE SEQUENCE 7.25 DYNAMIC VOLTAGE SWITCHING(DVS ···· 7.26 TEMPERATURE SENSOR 7.27 DUTY CYCLE CORRECTOR (DCC) ·· 8 OPERATING CONDITIONS 139 1 ABSOLUTE MAXIMUM RATINGS 139 8.2 PAD CAPACITANCES 8.3 PACKAGE ELECTRICAL SPECIFICATION .140 8.4 PACKAGE THERMAL CHARACTERISTICS 141 8.5 ELECTROSTATIC DISCHARGE SENSITIVITY CHARACTERISTICS 141 8. 6 ac DC OPERaTINg Conditions 142 8.7 POD I/O SYSTEM 147 8. 8 DD and IPP PARaMetERS and 'IES I CONDIIOns .150 8.9 AC TIMINGS 8.10 CLOCK-TO-DATA TIMING SENSITIVITY 8. 1.35VIO DRIVER MODELS 8.12 1.25VI/O DRIVER MODELS 9 PACKAGE SPECIFICATION 171 9.1 BALL-OUT 171 9.2 SIGNALS 172 9.3 ON DIE TERMINATION (ODT 9. 4 PACKAGE OUTLINE 9.5 x8 MODE ENABLE 9.6 PSEUDO-CHANNEL (PC) MODE 179 O IEEE 1149.1 BOUNDARY SCAN ·· 182 10.1 TEST PINS 10.2 TAP CONTROLLER ··*···· 10.3 TAP REGISTERS 10.4 TAP INSTRUCTION SET ..187 10.5 BOUNDARY SCAN OPERATION 10.6 INTERACTIONS BETWEEN BOUNDARY SCAN AND NORMAL DEVICE OPERATION 190 11 Annex A (informative) Differences between JESD250B and JESD250A JEDEC Standard No 250B GRAPHICS DOUBLE DATA RATE 6() SGRAM (From JEDEC Board ballot jCB-18-48, formulated under the cognizance of the jC-423C Letter Committee on DRAM Parametrics 1 SCOPE This document defines the graphics double data rate 6(Gddr6 Synchronous Graphics random access Memory(SGRAM) specification, including features, functionality, package, and pin assignments The purpose of this Specification is to define the minimum set of requirements for 8 Gb through 16 Gb x16 dual channel GDDr6 SGraM devices System designs based on the required aspects of this standard will be supported by all GDDR6 SGRAM vendors providing compatible devices. Some aspects of the GDDr6 standard such as AC timings and capacitance values were not standardized. Some features are optional and therefore may vary among vendors. In all cases, vendor data sheets should be consulted for specifics. This document was created based on some aspects of the gDDr5 Standard (EsD212) JEDEC Standard No 250B Page 2 GDDRO SGRAM STANDARD OVERVIEW 8 Gb 2 Channels 256Mbx 16 2x(16Mb 6 x 16 banks)/ 2 Channels 512Mb x8 2 X(32Mb x 8 x 1 6 banks 12 Gb =2 Channels 384Mb x 16 2x(24Mb x 16x 16 banks)/ 2 Channels 768Mbx8 2X(48Mbx8x 16 banks) 16 Gb =2 Channels 512Mb x 16 2 x(32Mb x 16 x 16 banks)/ 2 Channels 1Gb x8 2 X(64Mb 8 x 16 banks) 24 Gb-2 Channels 768Mbx 16 2x(48Mb x 16x 16 banks)/ 2 Channels 1.5Gbx8 2x(96Mbx8 x 16 banks 32 Gb 2 Channels 1Gb x 16 2x(64Mb x 16x 16 banks)/ 2 Channels 2Gbx8 2 x(128Mb x x 16 banks 2.1 FEATURES e 2 separate independent channels with point-to-point interface for data, address and command Half Ca data rate differential clock inputs CK_t/CK_c for CMD/ADD (CA)per 2 channels Four half data rate or quarter data rate differential clock inputs wck t/CK C, each associated with a data byte (DQ, DBI_n, EDC)or Two quarter data rate or half data rate differential clock input WCK_t/WCK_c,cach associated with the two bytes in the channel (vendor specific) Double Data Rate (DDR)or Quad Data Rate(QDR) data(with regards to the wCk)(Vendor specific) Double Data Rate(ddr)Command Address(with regards to the CK 16 internal banks e 4 bank groups for tcDl. -3 tcK and 4 tcK e 16n prefetch architecture: 256 bit per array read or write access per channel ● Burst length:16only Programmable READ latency: 9 to 36 tcK e Programmable WRITE latency: 5 to 8 tcK WRITE Data mask function via Ca bus(single/double byte mask Data bus inversion(DBi)& Command Address bus inversion (CaBl Input/output PLL/DLL on/off mode Command Address training: command address input monitoring by dQ/DBI_n/EDC signals wCK2CK clock training with phase information by edc signals Data read and write training via READ FIFO (depth 6) READ FIFO pattern preload by LDFF command e Direct write data load to read fifo by Wrtr command Consecutive read of read fifo by rdt command Read/ Write data transmission integrity secured by cyclic redundancy check using either a half or full data rate CrC READ/WRITE EDC on/off mode Programmable edc hold pattern for CDr a Programmable CRC rEad latency=1 to 4 tcK and CRC WRITE latency =10 to 16 tcK ● Low Power modes On-chip temperature sensor with read-out Auto precharge option for each burst access Auto refresh self refresh modes 32ms, auto refresh(16k cycles) e Temperature sensor controlled self refresh rate and Partial array Self Refresh Per-Bank/ Per-2-Bank Refresh e Optional digital tras lockout On-die termination(ODT) ODT and output driver strength auto-calibration with external resistor ZQ Programmable termination and driver strength offsets(40 ohm to 60ohm Internal VREF for data inputs and Ca inputs with programmable levels eparate internal VREF for CA (Command/ Address)inputs Vendor idi and id2 for identification x16/x8 mode configuration set at power-up with edc Pseudo-channel mode(PC mode) configuration set at power up with CA6 1.35V+/0.0405V supply for device operation (VDD 1.35V+/-0.0405V supply for IO interface(VDDo 1.8+0.108V/-0054 V supply for VpP 180 ball BGA package with 0. 75mm pitch JEDEC Standard No 250B 2.2 FUNCTIONAL DESCRIPTION The GDDR6 SGRaM is a high-speed dynamic random-access memory designed for applications requiring high bandwidth. GDDR6 devices contain the following number of bits 8 Gb has 8,589 934,592 bits 12 Gb has12,884901888bits 16 Gb has17,179869184bits 24 Gb has25769803,776bits 32 Gb has 34,359,, 368 bits The GDDR6 SGRAM's high-speed interface is optimized for point-to-point connections to a host controller On-die termination(ODT)is provided for all high-speed interface signals to eliminate the need for termination resistors in the system GDDR6 uses a 16n prefetch architecture and a ddR or QdR interface to achieve high-speed operation. The devices architecture consists of two 16 bit wide fully independent channels gDDR6 operates from a differential clock cK t and CK_ c CK is common to both channels. Command and Address(Ca) are registered at every rising edge of ck and every falling edge of CK. There are both single cycle and multi cycle commands. See command truth table for details GDDRo uses a free running differential forwarded clock (wck_t/wCK_c)with both input and output data registered and driven respectively at both edges of the forwarded wCK. See Clocking section for details Read and write accesses to gddro are burst oriented accesses start at a selected location and consists of a total of sixteen data words. accesses begin with the registration of an Activate command, which is then followed by a Read, Write(WOM)or masked Write(WDM, WSM)command The row and bank address to be accessed is registered coincident with the activate command. The address bits registered coincident with the Read, Write or masked Write command are used to select the bank and the starting column location for the burst access This specification includes all features and functionality required for GDDR6 SGRAM devices. In many cases the gDDr6 specification describes the behavior of a single channel JEDEC Standard No 250B Page 4 2.3 DEFINITION OF SIGNAL STATE TERMINOLOGY GDDR6 SGRAM will be operated in both Odt Enable(terminated) and ODT Disable(unterminated modes For highest data rates it is recommended to operate in the odt enable mode. ODT Disable mode is designed to reduce power and may operate at reduced data rates. There exist situations where ODT Enable mode can not be guaranteed for a short period of time, i.e, during power up Following are four terminologies defined for the state of a device(GDDro sGram or controller) signal during operation. The state of the bus will be determined by the combination of the device signal connected to the bus in the system. For example, in gDDro it is possible for the SGRAM pin to be tristated while the controller signal is HIGH or ODT. In both cases the bus would be HiGH if the ODT is enabled. For details on the device's signals and their function see Sections 9. 1 and 9.2 Device pin signal level HIGH: a device signal is driving the Logic"1"state e LOW: a device signal is driving the logic"o"state Hi-Z: A device signal is tristate ODT: A device signal terminates with OdT setting, which could be terminating or tristate depending on mode Register setting Bus signal level e HIGH: One device on bus is HiGH and all other devices on bus are either odt or Hi-Z. The voltage level on the bus would be nominally VDDQ e LOW: One device on bus is Low and all other devices on bus are either ODTor Hi-Z. The voltage level on the bus would be nominally Vol(dC if ODT was enabled, or Vss if Hi-Z. Hi-Z: All devices on bus are Hi-Z. The voltage level on bus is undefined as the bus is floating ODT: At least one device on bus is ODf and all others are Hi-Z. The voltage level on the bus would be nominally DDO 2.4 DEFINITION OF CLOCKING TERMINOLOGY Data refers to the signal being clocked(e. g. dQ by wCK and Ca by CK Half rate: clock is running at half of the data rate(e. g. WCK 4GHz and DQ at 8Gbps, or CK 1GHz and Ca at 2Gbps) Quarter rate: clock is running at a quarter of the data rate(e. g WCK 2GHz and DQ at 8Gbps Eighth rate: clock is running at one eighth of the data rate(. g WCK internal IGHz and DQ at 8Gbps DDR Double Data Rate): complement to half rate, referring to data relative to clock QDR(Quad Data Rate ): complement to quarter rate, referring to data relative to clock ODR (Octa Data Rate): complement to eighth rate, referring to data relative to clock

(系统自动生成,下载前可以参看下载内容)