DesignCon2019关于LPDDR5的资料PAPER_04_Electrical Integr

文件名称: DesignCon2019关于LPDDR5的资料

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详细说明：PAPER_04_Electrical Integrity for LPDDR5 Memory Technology.pdfntroduction Low Power Dual Data Rate(LPDDR)memory has been popular in low power devices such as handheld, smartphones, tablets, and low power notebooks. LPDDR2 specification first ratified by JEDEC in 2010. In 2012 JEDEC published first LPDDR3 spec, and in 2014 LPDDR4 was introduced LPDDR4x was introduced in 2016 and LPDDR5 spec will be published by jEdEC in 2019. Table 1 shows the speed comparison for these memories LPDDR2 LPDDR3 LP DDR4 LPDDR4X LPDDR5* JEDEC Spec 2010 2012 2014 2016 2019 Speed (MTPS 1033 2133 4267 4267 5400-6400* Table 1 features of lpddr memories JEDEC specification is not published yet, so we are just showing the trend Electrical System LPDDR5 electrical system representation is as shown in the following diagram Soc DRAM D e wwv MB Die PKg Pkg Figure 1 Block Diagram for SoC and LPDDR The figure shows the SoC LPDDR5 die, pkg and then Motherboard (Mb). this particular implementation shows BGA down version for the LPDDR5. The LPddr5 package is shown to be connected to the motherboard There are two major power domains for the LpDDr5 memory, one is vDDQ or final stage driver/receiver power domain and the other is vdd2 or dRAM core stage power domain the system designers need to meet the JEDEC specifications for these domains discussed in the next section Power Delivery Table 2 shows LP DDR memory voltage requirements and termination scheme for the final stage LPDDR2 LPDDR3 LPDDR4 LPDDR4X LPDDR5* Final stage 1.2 1.2 1.1 0.6 <0.6 voltage(v) DRAM Vdd2 1.2 1.2 1.1 1.1 core voltage DRAM Vdd1 8 1.8 1.8 1.8 1.8 Voltage Final stage Unterminated Unterminated/ Ground Ground Ground termination power termination termination termination* scheme terminated Speed(MTPS) 1033 21334267 4257 5400-6400* Table 2 LpDDR Specifications for different generations *JEDEC specification is not published yet, so we are just showing the trend Figure 2 shows the JEDEC specifications for the VDDQ voltage requirements(vim and Vmax) from LPDDR2 to lPddR4x LPDDR voltage trend 13 1.17 055 1.14 15 .57 160 110 LPDDR3 DDRA LPDDR5 Wmax-Vmin Budget (mv) vmin(t Vmax] Figure 2 LPDDR voltage tren As shown in the graph the vddQ min to max voltage is decreasing generation over generation(LPDDR3 to LPDDR4x to save the power. LPDDR5 Vmin-Vmax voltage estimates are projected based on the trend In order to meet these specification for LP DD R5 carefully design for different components including PMIc PCB and dimm card needs to be done PMIC/regulator DC accuracy ripple: The voltage set point at the regulator is depends on dc and ac components and the dc component further comprises of dc losses on board and package in addition to the dc accuracy of the voltage regulator since the regulation point can change with process, voltage and temperature, choosing a regulator with low dc variation has a direct impact on the a bility to meet the jedec spec at the memory ball and lowering power by setting it as low as possible PMIc/regulator load transient response The inherent nature of ddr loads is bursty and hence there is a corresponding load transient that the voltage regulator/PMIC will have to support Understanding the worst case load transient possible is the first step in determining how to deal with it the voltage budget assigned to transient dip and overshoot must be planned so that the final JEDEC specification is still met. In order to lower the voltage excursion due to a load transient there are several voltage regulator techniques popular in the industry today and it is usually a trade-off between transient performance spectral content and amount of board capacitance used Popular vr architectures employ automatic transitions between a high performance modeeg PWm)and a high efficiency mode at light loads (eg pfm) to deliver optimal efficiency across load conditions. this however usually implies worse transient performance when transitioning between these modes and can impact power adversely if the voltage has to be set higher to compensate for the larger dip in auto-mode of the regulator. Stack up of the PCB, and power shape routing: Losses on the board must be minimized in order to lower power and meet the JEDEC voltage specifications. The PCb must be designed carefully and the requirements to accomplish low path losses must be understood while deciding the stack-up and routing. Often, the ddr location is such that it is placed to optimize for signal integrity and power delivery into that section of the pcb is challenging In order to meet impedance targets, the materials used copper thickness and board shapes must be chosen accordingly. Type 4 PCB with buried/blind vias can be used for reducing the losses PMIc/regulator placement: The distance from PMic to the memory directly impacts the impedance irrespective of stack-up and conductive materials and so it is important to plan the placement of the pmic and the regulator so as to minimize losses. If the application permits a dual sided placement is beneficial allowing power to be delivered to the ddr from the other side of the board this however may not always be a possibility due to OEM requirements on form factor and cost Power Integrity For power integrity analysis, end-to-end system models are put together and frequency domain and time domain analysis is performed. The following section focuses on DRAM side analysis DRAM Die While LPDDR dram die and package models are not com monly available via the web they are available upon request under NDA. figure 3 shows an example of an equivalent pdn model for the lpddr die igure 3 Equivalent PDN model for the LPddR die On-die capacitor Cdie: On-die capacitance ESR: Resistance series to the cap. see earlier presentations) Power grid: Ldie: Power grid inductance Rdie: Power grid resistance Please note ESR and Rdie are separate. DRAM vendors may have monolithic or stacked die model Package Model Without going into supplier specific parameters, a generic metho dology is described in the following section. It shows the package model elements such as solder ball and bondwire. Quasistatic electromagnetic simulations can be done on the package layout and we can extract the resistance and inductance for the package. Figure 4 BGa balls and bondwire modeling The number of bga/bondwires assigned to VddQ and Vdd2 and ground will determine the equivalent r and L. It is desirable to reduce the r and l and assign more bga/bondwires as possible. For Signal Integrity this r and l will play important role at higher speeds Impedance profile for the DRAM Although, the r and l are extracted for the drAM model, for system level simulations, S parameters are used. Similar to the DRAM model, the motherboard model is simulated with quasistatic 3D or planar 3D solver and the s parameter model is generated. For the impedance analysis, die, package and motherboard models are put together are simulated Figure 5 shows the self-impedance plot for a generic DRAM. It shows two domains VddQ and vdd2 There are some variations in the package and the die and optimized model with lower impedance is plotted x Max:(100meg x Max:(1 05.15meg z11):H乙 z11(211_m z11(11r XMax:旧3.176meg x Max: (120.23meg z11):t :11g11m 211c211m 00 sOme 100m四g150me200me250m四3oomg (H2) Figure 5 Self Impedance for VddQ and vdd domains It should be noted that there is supplier process, die config fab variation in order of typical impact)and designs should take that into consideration. In this example the resonance frequency is shown to be around 107 hz for vddQ domain and around 120MHz for vdd2 domain Final stage currents VddQ Figure 6 shows the final stage current and noise simulation setup for the dram. there is a channel considered for the pdn simulations. at the buffer there are three currents: current from power to central node where transmission line is connected current to ground from that node and third one is final stage current Vcc-RX PDN GND Term PDN Vss-Rx Figure 6 Final Stage Current for LPDDR Noise simulations Since LpdDR5 information is not publically available, we cannot comment on actual excitation profiles but users can speculate based on commonly known info or such Some approximations are used and noise simulations are done for establishing the methodology. Here, the termination is at the ground current profiles are injected on the pdn model and noise simulations are done Figure 7 shows noise simulations at the LPDDR5 DRAM side, when the Soc is transmitting. There is termination to the ground so there is no direct power to ground current. However there is a current from transmission line to the ground. For this simulations planar 3D electromagnetic time domain solver is used. Transmission lines are used along with the power and ground structures. Currents are injected and we see noise across power and ground (shown in blue) for the dram w/simplified model 65mv WI SIPD model 67my SI Figure 7 vddQ noise simulations at dRAM It is difficult to use planar 3d electromagnetic solver with transmission lines every time we had to do Power integrity simulations. Therefore, an equivalent methodolo gy is established. Using some scaled current of transmission line to ground another current is derived from power to ground (at the dram) based on the decoupling capacitors. This current is injected from power to ground and the noise produced is shown in red color in Figure 7. the current magnitude is adjusted to match with the noise simulated earlier with transmission lines. In figure 7, both the simulations show similar magnitude but the noise signature is significantly different. Transmission line based pdn simulation results show much high frequency content. This illustrates that the entire system needs to be simulated for the LPDDR5 PDN analysis and we cannot ignore the ground current impact it is to be noted that the noise amplitude of 65mV is for generic example and levels may change dependent on the parameters Motherboard MEMORY RAIL PDN design Recommended Dc operating Conditions DRAM Symbol Min Max Unit N。tes Core 1 Power Do 170 1.80 1.95 1,2 Core 2 Power/Input Buffer powe DD 1.06 1.10 1.17 23 1/0 Buffer Power DDo 0.57 0.6 0.65 2,34,5 NOTE 1 VDD1 uses significantly less current than VDD2. NOTE 2 The voltage range is for DC voltage only. DC is defined as the voltage supplied at the DRAM and is inclusive of all noise up to 20 MHz at the DRAM package ball NOTE3 The voltage noise tolerance from DC to 20 MHz exceeding a pk-pk tolerance of 45 mv at the DRAM ball is not included in the TdIVw NOTE 4 VoDo(max) may be extended to 0.67 V as an option in case the operating clock frequency is equal or less than 800 Mhz NOTE 5 Pull up, pull down and zQ calibration tolerance spec is valid only in normal Vooo tolerance range .57v-0.65V Figure-8: LP4x Pl SPEC (Source: JEDEC LPDDR4X BALLOT, Item JC-426-183155 For LPDDR4X, dRAM Voltage noise bandwidth SPecs are defined at the dram bga ball from dc to 20 MHZ (Figure-8. The bandwidth /Max frequency is generally a consensus between the dram vendors and JEDEC Members. DRAM vendors publish the idd numbers but there is no easy way to derive the icc(t at the DRAM DIE/ BGA Designing an efficient Mb pdn will require the dRAm PKG PDN, DRAM CDIE/ RDIE, die level Icc(t)or a de-rated Icc(t)at the dRAM BGa ball. Without this information we potentially end up over/under designing the platform while we can get the icc(t)/dRAm PKg information from some vendors it is not representative of the industry and we cannot rely on this information to design the mb N Here is an example(Figure-9)showing the difference in the voltage noise seen at the drAm bga with/Without DRAM DIE/PKG PDN. (Note: DRAM DIE/PKG PDN is not a representative of any vendor It's an estimation based on commonly known information Vnoise WITHOUT DRAMPDN Vnoise WITH MOC DRAMPDN 1.12 Vnoise WITHOUT DRAMPDN -71 mv 1.1 Vnoise WITH DRAMPDN 6mV dY=627358m d=71.05836m DRAM ICCt 45 20MHz pulse Rise time 5ns 0 15n Figure-9(a: VDD2 Voltage noise waveform

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