ADC资料： ISSCC 2018ADC ISSCC18 会议近两年资料分享给大家 Outline

文件名称: ADC资料： ISSCC 2018

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上传时间: 2019-09-07

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详细说明：ADC ISSCC18 会议近两年资料分享给大家 ADC资料： ISSCC 2018Outline Motivation Dynamic error in feedback DAC Prior arts alleviating dynamic errors Inter-symbol-interference(ISI)error calibration TWO-step isI error measurement Analog domain compensation Hardware-saving digital excess loop delay(ELD)compensation Circuit implementation · Measurement resu|ts Conclusion 2018|EEE International Solid-State Circuits Conference 14.1: A 50MHzBW Continuous-Time 42 ADC with Dynamic Error Correction Achieving 798dB SNDR and 95.2dB SFDR 2of46 Motivations 75-- ·Left: SNDR VS.Fs 70 Bottom THD VS, Fs 65 60 65 55 80E+081.8E+0928E+093.8E+094.8E+095.8E+09 70 FS(Hz) -75 △Σ ADC in Murmann's ADC survey 80 ·BW>25MHz 85 Sampling Freq. > 800MHZ 90 80E+0818E+092.85+093.8E+094.8E+0958E+09 Fs (Hz) 2018|EEE International Solid-State Circuits Conference 14.1: A 50MHzBW Continuous-Time 42 ADC with Dynamic Error Correction Achieving 798dB SNDR and 95.2dB SFDR 3of46 Dynamic Error vs Sampling Frequency Vin Input stage of ctdSm ollowIng OP1 Stages Sensitive to nonidealities Dout DAC Ts Ts deal DAC output 2018|EEE International Solid-State Circuits Conference 14.1: A 50MHzBW Continuous-Time 42 ADC with Dynamic Error Correction Achieving 798dB SNDR and 95.2dB SFDR 4 of 46 Dynamic Error vs Sampling Frequency Input stage of CTDSM Following OP1 Stages Sensitive to nonidealities Dynamic errors happen Dout DAC during DAC transition Ts Strong signally dependent HTs Output w/Dynamic Error 2018|EEE International Solid-State Circuits Conference 14.1: A 50MHzBW Continuous-Time 42 ADC with Dynamic Error Correction Achieving 798dB SNDR and 95.2dB SFDR 5of46 Dynamic Error vs Sampling Frequency Vin Input stage of CTDSM Following OP 1 Stages Sensitive to nonidealities Dynamic errors happen Dout DAC during DAC transition Ts Strong signally dependent Ts ° mpact increases with Same sampling frequency Doul 2018|EEE International Solid-State Circuits Conference 14.1: A 50MHzBW Continuous-Time 42 ADC with Dynamic Error Correction Achieving 798dB SNDR and 95.2dB SFDR 6of46 Sources of Dynamic Errors Synchronized Current output CTRLS Fs Quantizer Output DAC<1> < DAC<2> lout D<2 Q DAC<3> D<3 2018|EEE International Solid-State Circuits Conference 14.1: A 50MHzBW Continuous-Time 42 ADC with Dynamic Error Correction Achieving 798dB SNDR and 95.2dB SFDR 7of46 Sources of Dynamic Errors Current Output Fs Quantizer Output DAC<1> D<1> Q D DAC<2> lout D<2> DAC<3> D<3> Mismatches in DFFs, switches and parasitics along the routings 2018|EEE International Solid-State Circuits Conference 14.1: A 50MHzBW Continuous-Time 42 ADC with Dynamic Error Correction Achieving 798dB SNDR and 95.2dB SFDR 8of46 Phase mismatch vs.sI Error DAC output w/ DAC output w/ Phase MM ISI error Ts DAC <1> - Ts DAC <1> output output DAC <2> Ts DAC <2> i output utput DAC <3> DAC <3> output output T1 T2 T1 T2 T3 Phase mismatch error got high-pass filtered Impact of isi error is more significant 2018|EEE International Solid-State Circuits Conference 14.1: A 50MHzBW Continuous-Time 42 ADC with Dynamic Error Correction Achieving 798dB SNDR and 95.2dB SFDR 9of46

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