JESD79-4 DDR4 SDRAM标准.pdfDDR4标准，库里下载积分太高啦，不便于大家共享资

文件名称: JESD79-4 DDR4 SDRAM标准.pdf

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详细说明：DDR4标准，库里下载积分太高啦，不便于大家共享资源，重新传一份，可惜我没有4B，哈哈PLEASEI DONT VIOLATE THE LAW This document is copyrighted by JEDECand may not be reproduced without permission For information contact JEDEC Solid State Technology Association 3103 North 1oth street, suite 240 South Arlington, Virginia 22201-2107 or call(703)907-7559 JEDEC Standard no, 79-4 DDR4 SDRAM STANDARD (From JEDEC Board Ballot JCB-12-40, formulated under the cognizance of the JC-42 3 Subcommittee on DRAM Memories. Contents 1. Scope 2. DDR4 SDRAM Package Pinout and Addressing 2.1DDR4 SDRAM RoW for×4,8and×16 2.2 DDR4 SDRAM Ball Pitch 2222 2.3 DDR4 SDRAM Columns for X4x8 and x16 2 2.4 DDR4 SDRAM X4/8 Ballout using Mo-207 2 2.5DDR4 SDRAM X16 Ballout using Mo207……… 3 2.6 Pinout Description 2.7 DDR4 SDRAM Addressing .7 3. Functional Description “·“ 8 3. 1 Simplified State Diagram .8 3.2 Basic Functional 3. 3 RESEt and initialization procedure Initialization s 0 3.3.2 Reset initialization with stable powel 11 3.4 Register Definition 12 3.4. 1 Programming the mode registers 2 3.5 Mode Register 13 4. DDR4 SDRAM Command Description and Operation 24 4.1 Command truth table 24 4.2 CKE Truth table 25 4.3 Burst Length, Type and Order 26 4.3.1 bl8 burst order with crc enabled 4.4 DLL-off Mode dll on/off Switching procedure 4.4.1 DLL on/off switching procedure 4.4.2 DLL"on” to dll“o” Procedure 27 4.4.3DLL“ off to dll“on, Procedure 8 4.5 DLL-off mode .29 4.6 Input Clock Frequency Change 30 4.7 Write Leveling………… 31 4.7.1 DRAM setting for write leveling DRAM termination function in that mode 32 4.7.2 Procedure Description 4.7. 3 Write Leveling mode Exit 面能 4.8 Temperature controlled Refresh modes 34 4.8. 1 Normal temperature mode 34 4.8.2 EXtended temperature mode 4.9 Fine Granularity Refresh Mode 35 4. 9. 1 Mode register and command Truth Tabl 35 4.9.2 tREFI and tRFC parameters 5 4.9.3 Changing Refresh Rate 4.9.4 Usage with temperature controlled Refresh mode 4.9.5 Self Refresh entry and exit 37 4.10 Multi Purpose Register 37 4.10.1 DQ Training with MPR 4.10.2 MR3 definition ∴37 4.10.3 MPR Reads 38 4.10.4 MPR Writes 4.10.5 MPR Read Data format 43 4.11 Data Mask(DM), Data Bus Inversion(DBI) and TDQs 48 4.12 ZQ Calibration Commands 50 JEDEC Standard no, 79-4 4.12.1 ZQ Calibration Description 50 4.13 DQ Vref Training 51 4. 14 Per DRAM Addressability 56 4.15 CAL Mode(cs_ n to Command Address Latency) 5 4.15.1 CAL Mode Description 59 4. CRC 4. 16. 1 CRC Polynomial and logic equation 61 4.16.2 CRC data bit mapping for x8 devices 63 4. 16.3 CRC data bit mapping for x 4 devices 63 4.16. 4 CRc data bit mapping for x16 devices 63 4.16.5 Write CRC for x4, x8 and x16 devices .64 4.16.6 CRC Error Handling .64 4.16.7 CRC Frame format with bc4 65 4.16. 8 Simultaneous DM and CRC Functionality 4. 17 Command Address Parity( CA Parity 68 4. 17. 1 CA Parity Error Log Readout 74 4.18 Control gear down mode 4. 19 DDR4 Key Core Timing 77 4.20 Programmable Preamble 80 4.20.1 Write Preamble 80 420.2 Read Preamble 81 4.20.3 Read Preamble Training ...... 82 4.21 Postamble 82 421.1 Read Postamble 82 4.212 Write Postamble 82 4.22ACTⅣ ATE Command 82 4.23 Precharge Command 83 4.24 Read operation 83 4.24.1 READ Timing Definitions 83 4.24.1.1 READ Timing; Clock to Data Strobe relationship 85 4. 24.1.2 READ Timing; Data Strobe to Data relationship 4. 3 tLZ(DQS), tLZ (DQ), tHz(DQS), tHZ(DQ)Calculation 87 4.24.1. tRPRE Calculation 88 4.24.1.5 tRPST Calculation 89 4.24.2 READ Burst Operation 4.24.3 Burst Read Operation followed by a Precharge 101 4.24. 4 Burst Read Operation with Read dBi(Data Bus Inversion) 103 4.24.5 Burst Read Operation with Command/Address Parity ...... 104 4.24. 6 Read to write with write crc 105 4. 24.7 Read to Read with CS to CA Latency.. 106 4.25 Write Operation..... 107 4.25. 1 Write Burst operation 107 4.26 Refresh Command 123 4.27 Self refresh Operation 124 4.271 Low Power auto self Refresh 126 4.28 Power down mode .127 4.28. 1 Power-Down Entry and Exit 127 428.2 Power-Down clarifications 132 4.29 Maximum Power Saving Mode 132 4.29. 1 Maximum power saving mode ..132 4.29.2 Mode entry……… ..132 4.29.3 CKE transition during the mode 133 429. 4 Mode exit 134 4 0. 29.5 Timing parameter bin of Maximum Power Saving Mode for DDR4-1600/1866/2133/2400/2666/3200 134 Connectivity Test Mode .135 430.1 Introduction 135 4.30.2 Pin Mapping… 135 4.30.3 Logic Equations… 136 4.30.3. 1 Min Term Equations 136 JEDEC Standard no. 79-4 4.30.3.2 Output equations for x16 devices 136 4.30.3. 3 Output equations for X8 devices 136 4.30.3. 4 Output equations for X4 devices 4.30.4 T iming Requirement 137 4.31 CLK to Read dQs timing parameters…… 137 5. On-Die Termination 139 5. 1 ODT Mode Register and odt State table....... ::“ 139 5.2 Synchronous ODT Mode…… 1 ..141 5.2. 1 ODT Latency and Posted ODT 142 5.2.2 Timing Parameters 142 5.2. 3 OdT during Reads 143 5.3 Dynamic ODT 144 5.3.1 Functional Description .144 5.3.2 ODT Timing Diagrams 145 5. 4 Asynchronous odT mode 146 5.5 OdT buffer disabled mode for power down 147 5.6 ODT Timing definitions 148 5.6.1 Test Load for odt timings 148 5.6.2 ODT Timing Definitions 148 6. Absolute Maximum Ratings 150 7.AC& DC Operating Conditions…… 151 7.1 AC and dc Input Measurement Levels: VREF Tolerances 151 7.2 AC and DC Logic Input Levels for Differential Signals 152 7.2.1 Differential signal definition .152 7.2.2 Differential swing requirements for clock(CK_t-CK_c) 152 7.2.3 Single-ended requirements for differential signals “ 153 7.2.4 Address and Control Overshoot and Undershoot specifications 153 7.2.5 Clock Overshoot and Undershoot specifications 154 7.2.6 Data, Strobe and Mask Overshoot and Undershoot Specifications 7.3 Slew Rate Definitions for Differential Input Signals(CK) 155 7.4 Differential Input Cross Point Voltage 156 7.5 CMOS rail to rail input levels 158 7.5. 1 CMOS rail to rail Input Levels for RESEt n 158 8. AC and dc output Measurement levels .159 8.1 Output Driver DC Electrical CharacteristIcs 159 8.1.1 Alert n output Drive Characteristic 160 8.2 Single-ended AC& DC Output Levels .161 8.3 Differential AC DC Output Levels .161 8.4 Single-ended Output Slew Rate 161 8.5 Differential Output slew Rate 162 9. Speed Bin… 163 9.0. 1 Speed Bin Table Note 167 10. IDD and iddQ Specification Parameters and Test conditions 168 10.1 IDD. IPP and IDDQ Measurement Conditions 168 10.2 IDD Specifications 183 11. Input/Output Capacitance 185 12. Electrical Characteristics AC Timing 187 12.1 Reference Load for AC Timing and output slew Rate 187 12.2 tREFI 187 12.3 Timing Parameters by Speed Grade 12. 4 The DQ input receiver compliance mask for voltage and timing is shown in the figure below 198 12.5 DDR4 Function matri 203 JEDEC Standard no, 79-4 JEDEC Standard no, 79-4 Page 1 Se cope This document defines the DDR4 SDRAM specification, including features, functionalities, AC and dc characteristics, packages, and ball/signal assignments. The purpose of this Standard is to define the minimum set of requirements for JEDEC compliant 2 Gb through 16 Gb for x4, X8, and x16 DDR4 SDRAM devices. This standard was created based on the DDR3 standardn ( JESD79-3)and some aspects of the DDR and dDR2 standards JESD79, JESD79-2 these ballots were then incorporated to prepare this JESD79-4 specifications, replacing whole sections and incorporating the onof Each aspect of the changes for DDR4 SDRAM operation were considered and approved by committee ballot(s). The accumulatio changes into Functional Description and Operation JEDEC Standard no, 79-4 Page 2 DDR4 SDRAM Package Pinout and Addressing 2.1 DDR4 SDRAM Row for X4 x8 and X16 The DDR4 SDRAM X4 8 component will have 13 electrical rows of balls. Electrical is defined as rows that contain signal ball or power/ground balls. There may be additional rows of inactive balls for mechanical support The DDR4 SDRAM X16 component will have 16 electrical rows of balls. There may be additional rows of inactive balls for mechanical 2.2 DDR4 SDRAM Ball Pitch The DDR4 SDRAM component will use a ball pitch of 0. 8 mm by 0.8 mr The number of depopulated columns is 3 2.3 DDR4 SDRAM Columns for X4. 8 and x16 The DDR4 SDRAM X4/x8 and x16 component will have 6 electrical columns of balls in 2 sets of 3 columns There will be coulmns between the electrical columns where there are no balls populated. The number of these columns is 3 Electrical is defined as columns that contain signal ball or power/ground balls. There may be additional columns of inactive balls for mechanical support 2. 4 DDR4 SDRAM X4/8 Ballout using Mo-207 2 3 45|6 8 9 DM n DbI n VDD VSSQ TDQS c TDQS sQ vS (NC) B VPP VDDQ DOS c DQ1 VDDQ ZQ B VDDQ DQ0 Das t VDD VSS VDDQ DQ4 DQ5 VSSQ DQ2 DQ3 VSSQ (NC) (NC) DQ6 DQ7 VSS VDDQ (Nc)1 VDDQ VSS E (NC) VDD (c2)5 ODT CK t CK C VDD ODT1 VSS (CO)5 CKE cs n (c1) TEN CKE1 6 (NC VDD WE n Act n CAS n RAS A14 A15 A16 VSS H VREFCA BGO A10 A12 AP Bc n BG1 VDD K VSS BAO A4 A3 BA1 VSS K RESET n A6 AO A1 A5 AleRT n VDD A8 A2 A9 A7 VPP M VSS A17 A11 PAR A13 VDD N (NC) NotE 1 These pins are not connected for the X4 configuration NotE2 TDQs t is not valid for the x4 configuration NotE 3 TDQS c is not valid for the x4 configuration NotE 4 A17 is only defined for the x4 configuration NOTE 5 These pins are for stacked component such as 3DS. For mono package, these pins are NC NoTE6 ODT1 /CKE1 /CS1 n are used together only for DDP NOTE7 TEN is optional for 8Gb and above. This pin is not connected if Ten is not supported gure 1 DDR4 Ball Assignments for the x4/8 component

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