文件名称:
arvell-phys-transceivers-alaska-88e151x-datasheet--1360912.pdf
开发工具:
文件大小: 1mb
下载次数: 0
上传时间: 2019-09-04
详细说明：Marvell 88E151X芯片手册，适用于1000Base-T的以太网接口MARVEL LO
Marvell. Moving Forward Faster
M EL
TheA|aSka88E1510/88E1518/88E151288E1514
The device incorporates the Marvell Advanced Virtual
device is a physical layer device containing a single
Cable Tester(Vct )feature, which uses Time Domain
10/100/1000 Gigabit Ethernet transceiver. the
Reflectometry(tdR)technology for the remote
transceiver implements the Ethernet physical layer
identification of potential cable malfunctions, thus
portion of the 1000BASE-T, 100BASE-TX, and
reducing equipment returns and service calls. Using
10BASE-T standards. It is manufactured using standard vct, the alaska device detects and reports potentia
digital Cmos process and contains all the active circuitry cabling issues such as pair swaps, pair polarity and
required to implement the physical layer functions to
excessive pair skew. The device will also detect cable
transmit and receive data on standard cat 5 unshielded
opens shorts or any impedance mismatch in the cable
twisted pair
and reporting accurately within one meter the distance to
The device supports the RGMiI(Reduced pin count
the fault
GMIl)and SGMII for direct connection to a MAC/Switch
The device uses advanced mixed-signal processing to
port. The SGMl can also be used on media/line side to perform equalization, echo and crosstalk cancellation
connect to SFP modules that support 1000BASE-X
data recovery, and error correction at a Gigabits per
100BASE-FX and SGMIl. It also supports Copper/Fiber second data rate. The device achieves robust
Auto-media applications with RGMll as the MAc
performance in noisy environments with very low power
interface SGMII operates at 1.25 Gbps over a single
dissipation
differential pair thus reducing power and number of l/Os
used on the mac interface
The device integrates mdi termination resistors into the
10/100/1000BASE-T IEEE 802.3 compliant
PHY. This resistor integration simplifies board layout and
Multiple Operating Modes
reduces board cost by reducing the number of external
RGMII to Copper
components The new Marvell calibrated resistor
scheme will achieve and exceed the accuracy
SGMII to Copper(88E1512/88E1514 device
requirements of the IEEE 802.3 return loss
specifications
RGMII to Fiber/SGMII(88E1512 device only)
RGMII to Copper/Fiber/SGML with Auto-Media
The device has an integrated switching voltage regulator
Detect(88E1512 device only)
to generate all required voltages. The device can run off
Copper to Fiber(1000BASE-X)
a single 3.3V supply. The device supports 1.8V,2.5V,
88E151288E1514
and 3. lvcmos vo standards
a Four RGMl timing modes including integrated
The88E151088E1518/88E1512/88E1514 device
delays- This eliminates the need for adding trace
supports Synchronous Ethernet(SyncE)and Precise
delays on the Pcb
Timing Protocol (PTP)Time Stamping, which is based on Supports 1000BASE-X and 100BASE-FX on the
lEEE1588 version 2 and IEEE802.AS
Fiber interface along with SGMII(88E1512 device
The88E1510/88E1518/88E1512/88E1514 device
Supports LVCMOS lO Standards on the RGMIl
supports iEEE 802. 3az-2010 Energy Efficient Ethernet
(EEE)and is IEEE 802. 3az-2010 compliant
Copyright⊙2018 Marvell
Doc. No, MV-S107146-U0 Rev B
February 23, 2018
Document Classification Public
Page 3
MARVE L LG
Supports Energy Efficient Ethernet(EEE)-IEEE
Automatic Mdi/MDIX crossover at all speeds of
802. 3az-2010 compliant
operation
EEE Buffering
Automatic polarity correction
Incorporates EEE buffering for seamless support
lEEE 802.3 compliant Auto-Negotiation
of legacy MACs
Software programmable LEd modes including LED
Ultra Low power
testing
Integrated MDI termination resistors that eliminate
MDC/XMDIO Management Interface
passive components
CRC checker, packet counter
Integrated Switching Voltage Regulators
Packet generation
Supports Green Etherne
Wake on LAN ( WOL)event detection
Active Power save Mode
Advanced Virtual Cable Tester(VCT
Energy Detect and Energy Detect+ low power
Auto-Calibration for mac Interface outputs
modes
Temperature Sensor
IEEE1588 version 2 Time Stamping
Supports single 3. 3v supply when using internal
Synchronous Ethernet (SyncE) Clock Recovery
SWItching regulator
Three loopback modes for diagnostics
1/0 pads can be supplied with 1.8V,2.5v, or 3. 3V
Downshift mode for two-pair cable installations
Commercial grade, Industrial grade(88E1510 and
a Fully integrated digital adaptive equalizers, echo
88E1512 only
cancellers and crosstalk cancellers
a 48-Pin QFN 7 mm x 7 mm Green package with
Advanced digital baseline wander correction
EPAD(88E1510 and 88E1518 and 56-Pin QFn 8
nm x 8 mm Green package with EPAD
(88E1512/88E1514 device
RGMII to Copper
es
Ye
Ye
N
SGMII to Copper
No
No
Yes
Yes
RGMII to Fiber/sgml
No
NO
Yes
No
RGMII to Copper/Fiber/SGMII with Auto-Media Detect
Ye
N
Copper to Fiber
No
Yes
Yes
1/0 Voltage(VDDO)
33V2518ony3M5/18325W/18y
EEE 802.3az-2010 Energy Efficient Ethernet(EEE)
Yes
Yes
es
EEE Buffering
Ye
Yes
Yes
Yes
Synchronous Ethernet (SyncE)
Yes
Yes
Yes
Precise Timing Protocol(PTI
Yes
Yes
Auto-Media detect
No
No
Yes
Wake on LAN (WOL
Yes
Yes
Yes
Yes
Package
48-pin QFN
56-pin QFN
Industrial/Commercial Temperature
Commercial Commercial Commercial
Commercial
Industrial
Industrial
Doc. No MV-s107146-U0 Rev B
Copyright ( 2018 Marvell
Page 4
Document Classification Public
February 23, 2018
MAC Interface Alaska
88E1510
Media Type
10/100/1000Mbps
RGMII
88E1518/3
①
RJ-45
10BASE-T
Ethernet mac
100BASE-TX
88E1512
1000BASE-T
Device
MAC Interface
Alaska
Media type
10/100/1000 Mbps SGMI/SERDES 88E1512/
10BASE
Ethernet mac
RJ-45
88E1514
100BASE-TX
Device
1000BASE-T
MAC Interface
Alaska. SERDES
Media Type
10/100/1000Mbps
RGMI
A t SGMII
Ethernet mac
88E1512
Fiber-1000BASE-X
Device co
OptIcs
100BASE-FX
SFP
Media Type
SERDES/SGMIl Fiber -1000BASE-X
MAC Interface
Alaska a d
Optics-100BASE-FX
0/100/1000Mbps
RGMII
Ethernet mac
88E1512三
SFP
Device
Media Type
RJ-45-1000BASE-T
100BASE-TX
10BASE-T
Copyright⊙2018 Marvell
Doc. No, MV-S107146-U0 Rev B
February 23, 2018
Document Classification Public
MARVEL LO
1.1
Pin Description
88E1510/88151848 Pin QFN Package Pinout∴…
18
88E1512 56-Pin QFN Package Pinout
23
1.1.3 88E1514 56-Pin QFN Package Pinout
1.2
Pin assignment Lis
1.2.1 88E1510 48-Pin QFN Pin Assignment List- Alphabetical by Signal Name
1.2.2 88E1518 48-Pin QFN Pin Assignment List- Alphabetical by Signal Name
1.2.3 88E1512 56-Pin QFN Pin Assignment List-Alphabetical by Signal Name
35
1.2.4 88E1514 56-Pin QFN Pin Assignment List- Alphabetical by Signal Name
.36
2.1
Modes of operation and major Interfaces
37
2.2
Copper Media Intertace……………………
39
2.2.1 Transmit Side Network Interface
39
2.2.1.1
Multi-mode TX Digital to Analog Converter
2.2.1.2
Slew Rate Control and Waveshaping
40
2.2.2 Encoder
2.2.2.1
1000BASE-T
1面面
40
2.2.2.2
100BASE-TX
2.2.2.3
10BASE-T
2.2.3 Receive side network Interface
2.2.3.1
Analog to Digital Converter……
40
2.2.3.2
Active Hybrid
40
2.2.3.3
Echo canceller
40
2.2.34
NEXT Cance|er∴
40
2.2.3.5
Baseline Wander canceller
4
2.2.3.6
Digital Adaptive equalizer
2.2.3.7
Digital Phase Lock Loop
41
2.2.3.8
Link monitor
2.2.3.9
Signal Detection….
41
2.2.4 Decod
41
2.2.4.1
1000BASE
2.2.4.2
100BASE-TX
42
2.24.3
10BASE-T
42
2.3 1.25 GHz SERDES Interface
42
2.3.1 Electrical Interface
42
24
MAC Interfaces
24.1sGM|
43
2.4.1.1
SGMII Speed and Link
2.4.1.2
SGMII TRR Blocking.....
24.1.3
False sERDES Link Up Preventi0n.……
4
242 RGMIl
2.4.3 10/100 Mbps Functionality
45
2.4.4 TX ER and RX ER Coding
2.5
loopback
45
2.5. 1 System Interface Loopback
Doc. No, MV-s107146-U0 Rev B
Copyright ( 2018 Marvell
P
Document Classification Public
February 23, 2018
2.5.2 Line Loopback
2.5.3 External Loopback
2.6
Resets
49
2.7
Power Management…
49
2.7.1 Low Power modes
49
2.7.1.1
IEEE Power Down mode
50
2.7.1.2
Copper Energy Detect Modes
50
2.7.2 RGMI SGMII MAC Interface power down
2.8 Auto-Negotiation
2.8.1 10/100/1000BASE-T Auto-Negotiation
52
2.8.2 1000BASE-X Auto-Negotiation
2.8.3 SGMII Auto-Negotiation
.53
2.8.3.1
Serial Interface Auto-Negotiation Bypass Mode
2.9
CRC Error counter and frame counter
54
2. 9. 1 Enabling the CRC Error Counter and packet Counter
2.10 Packet generator
54
2. 1.25G PRBS Generator and checker
111面ci
a面
5
2.12 MDI/MDIX Crossover
56
2.13 Polarity Correction
56
2.14 FLP Exchange Complete with No Link……
57
2.15 Duplex Mismatch Indicator
57
2.16
58
2.16.1
ED Polarity……
59
2.16.2 Pulse Stretching and Blinking
59
2.16.3 Bi-Color LEd Mixing
.60
2.16.4 Modes of Operation
62
2.16.4.1
Compound LED Modes
2.164.2
Speed Blink
63
2.164.3
Manual override
63
2.16.44 MODE 1 MODE 2 MODE 3 MODE 4
64
2.17 Interrupt
.64
2.18 Configuring the 88E1510/88E1518/88E1512/88E1514 Device
65
2. 18. 1 Hardware Configuration
∴…65
2. 18.2 Software Configuration-Management Interface
66
2.18.2.1
Preamble Suppression
2.19 Jumbo Packet Support
2.20 Temperature Sensor
67
2.21 Regulators and Power Supplies
68
2.21.1AVDD18
68
2.21.2 AVDDO18
68
2.21.3AVDD33
68
2.21. 4 DVDD
69
2.21.5REG|N
69
2,21.6 AVDD18 OUT
69
2.217 DVDD OUT
9
2.21.8VDDo
69
2.21. 9 Power Supply sequencing
69
Copyright⊙2018 Marvell
Doc. No, MV-S107146-U0 Rev B
February 23, 2018
Document Classification Public
Page 7
MARVE LL
PHY MDIO Register Description
70
4.1 Absolute Maximum Ratings
118
4.2 Recommended Operating Conditions.......
119
4.3
Package Thermal Information
120
4.3.1 Thermal Conditions for 88E1510/88E1518 48-pin, QFN Package
120
4.3.2 Thermal Conditions for 88E1512/88E1514 56-pin, QFN Package
12
4. 4 88E1510/88E1518 Current Consumption
4. 4. 1 Current Consumption when using EXternal Regulators
4.4.2 Current Consumption when using Internal Regulators
4.5 88E1512 Current Consumption
124
4.5.1 Current Consumption when using EXternal Regulators
124
4.5.2 Current Consumption when using Internal Regulators
126
88E1514 Current Consumption
127
4.6.1 Current Consumption when using EXternal Regulators
127
4.6.2 Current Consumption when using Internal Regulators
128
4.7
DC Operating Conditions
129
4.7.1 Digital Pins
4.7.2 EEE DC Transceiver parameters
4.8
AC Electrical specifications
4.8.1 Reset Timing
131
4.8.2 XTAL INXTAL OUT Timir
132
4.8. 3 LED to CONFIG Timing
133
4.9
SGMII Timing
...........
134
4.9.1 SGMII Output AC Characteristics
134
4.9.2 SGMII Input AC Characteristics
134
4. 10 RGMII Timing
135
410.1 RGMIl AC Characteristics
135
4.10.2 RGMll Delay Timing for different RGMll Modes
136
4.10.2.1
PHY Input - CLK Delay when Register 21_ 2.4=0
4.10.2.2
PHY Input -TX CLK Delay when Register 21 2.4=1
136
4.10.2.3
PHY Output -RX CLK Delay
.137
4.10.24
PHY Output- RX CLK Delay……
137
4.11 MDC/MDIO Timing
138
4.12
EEE Ac Transceiver parameters
139
4.13 Latency Timing
.140
4.13. 1 RGMiI to 1000BASE-T Transmit Latency Timing
140
4.13.2 RGMII to 100BASE-TX Transmit Latency Timing
140
4.13.3 RGMII to 10BASE-T Transmit Latency Timing
140
4.13.4 1000BASE-T to RGMII Receive Latency Timing
141
4.13.5 100BASE-TX to RGMll Receive Latency Timing
141
4.13.6 10BASE-T to RGMll Receive Latency Timing
141
4.13.7 10/100/1000BASE-T to SGMII Latency Timing
4.13.8 SGMII to 10/100/1000BASE-T Latency Timing
142
5.1
48-Pin QFN Package
.143
Doc. No MV-s107146-U0 Rev B
Copyright ( 2018 Marvell
Page 8
Document Classification Public
February 23, 2018
5.2
Pin QFn Package…
145
6.1
Part Order Numbering…
147
62 Package Marking…
149
6.2.1 Commercial
149
6.2.2 ndustrial
Copyright⊙2018 Marvell
Doc. No, MV-S107146-U0 Rev B
February 23, 2018
Document Classification Public
Page 9
MARVEL LO
Table 1: 88E1510/88E1518/88E1512/88E1514 Device Features
Table 2: Pin Type Definitions
17
Table 3: Media dependent Interfa
,19
Table 4
RGMII
20
Table 5: Management Interface and Interrupt
,,,,,
Table 6: LED Interface
Table 7
Clock/Configuration/Reset//o
Table 8: Control and reference
Table 9: Test
2222
Table 10: Power, ground Internal Regulators
Table 11: Media Dependent Interface
Table 12: RGmll
Table 13: Management Interface and Interrupt.
25
Table 14: lED Interface
Table 15: Clock/Configuration /Reset//0
Tabe16:SGM||Os…
Table 17: Control and reference
26
Table 18: Test
26
Table 19: Power, Ground, and Internal Regulators
.27
Table 20: Media dependent Interface
29
Table 21: Management Interface and Interrupt
30
Table 22: LEd Interface
.30
Table 23: Clock/Configuration/Reset//O
30
Table 24 SGMl l/os
30
Table 25: Control and reference
Table 26 test
iaaeaaaaaat
Table 27: Power, ground, and internal regulators
Table 28 No connect
““
32
Table 29: 88E1510 48-Pin QFN Pin Assignment List- Alphabetical by Signal Name
Table 30: 88E1518 48-Pin QFN Pin Assignment List- Alphabetical by Signal Name
34
Table 31: 88E1512 56-Pin QFN Pin Assignment List- Alphabetical by Signal Name
Table 32: 88E1514 56-Pin QFN Pin Assignment List- Alphabetical by Signal Name
36
Table 33: MODE[2: 0] Select
.39
Table 34: SGMIl (System Interface)Operational Speed
Table 35: Fiber noise Filtering
43
Doc. No, MV-s107146-U0 Rev B
Copyright ( 2018 Marvell
P
Document Classification Public
February 23, 2018
(系统自动生成,下载前可以参看下载内容)
下载文件列表
相关说明
- 本站资源为会员上传分享交流与学习,如有侵犯您的权益,请联系我们删除.
- 本站是交换下载平台，提供交流渠道，下载内容来自于网络，除下载问题外，其它问题请自行百度。
- 本站已设置防盗链，请勿用迅雷、QQ旋风等多线程下载软件下载资源，下载后用WinRAR最新版进行解压.
- 如果您发现内容无法下载，请稍后再次尝试；或者到消费记录里找到下载记录反馈给我们.
- 下载后发现下载的内容跟说明不相乎，请到消费记录里找到下载记录反馈给我们，经确认后退回积分.
- 如下载前有疑问，可以通过点击"提供者"的名字，查看对方的联系方式，联系对方咨询.
