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详细说明：小数分频VHDL代码.pdf
(145.33 KB, 下载次数: 249 )d arch
2:fdn,任意整数分频器(分步系数2--15,可自行修改代码増增加分频系数)
library ieee
use ieee std logic 1164.all
use ieee std logic unsigned. all
entity fdn is
port
lock in
std log
enable
in std logic
n of fd
in std logic vector (3 downto 0)
clock out: out std⊥
end entit
architecture bhy of fdn is
signal clock
std logic
signal g0
td logi
signal q1
std logic
signal number std logic vector(2 downto 0)
signal counter0: std logic vector(3 downto 0)
signal counter: std logic vector(3 downto 0)
beg
fdn: process(enable, clock in, n of fd, clock, g0, q1)
begin
number (2 downto 0)<=n of fd (3 downto 1)
I gl=0 then
clock not clock in
else
clock clock in
end if:
if (enable'1)then
if (n of fd(0)=0)then
counter1(-(others->'0')
f rising edge(clock in)then
if (number=001")then
10= not gO
else
if countero= number- then
counter0<-(others->'0'
0
not q0
e⊥se
countero<= countero +1
end if.
end⊥
end if
countero <-(others->'0)
gO
0
if rising edge(clock) the
if counter1= number then
counter<=(others=>'0')
1 < not ql
else
counter counter1+ 1
end if
end if
end if
se
10<='0
q1<=
0
counter0(=(others=>'0)
counter1 <-(others>0)
end if
end process fdn
output: process (enable, n of fd(0), g0, g1)
begin
if(enable='1')then
if(n of fd(0)0)then
clock out < g0
else
clock out ql
end il
ese
lock out(=0
end if
end process output
end bh
3:sel,分频器选择信号判断六生器
library ieee
use ieee std logic 1164. all
use iece. std logic arith. all
use ieee std logic unsi gned all
entity sel is
port
clock in
ogle
Xnumber: in std logic vector (3 downto 0)
sel out out std logic
end entity
architecture bhy of sel is
signal XsubTen std logic vector (3 downto 0)
sIgnal g
std logic vector(4 downto O)
b
eg
XsubTen < 10- Xnumber
sel: process(clock in, g)
beg
if (clock in event and clock in='0')then
if q+ xsubTen >=10 then
q<=q+Ⅹ subTen-10
else
q<=q+Ⅹ subten;
end if
d if
f g>= Xnumber then
sel out<=’0
else
sel out =1
d if:
end process sel
d bht
4:mux21,2选1数据选择器
library ieee
use iece std logic 1164. all
entity mux 21 is
port(
a: in std logic;
b: in std logic
s: in std logic
out std logic
end entity
architecture bhy of mux 21 is
begin
with s select
y< a when 1
b when others
end bhy
5: number,分频器系数处理器
library ieee
use ieee std logic 1164. all
use ieee std logic unsi gned all
entity number is
port
n
in std logic vector(3 downto 0)
number: out std logic vector (3 downto 0)
number: out std ogic vector (3 downto 0)
end entity
architecture bhy of number is
begin
number0<-n
number1 < n+1
end bh
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