LPDDR4_Spec.pdf从JEDEC官网下载，目前市面是最完整版本。本人从事一线DDR芯片设计

文件名称: LPDDR4_Spec.pdf

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详细说明：从JEDEC官网下载，目前市面是最完整版本。本人从事一线DDR芯片设计，欢迎交流：919726264qq.comLPDDR4 Specification Revision B Item 1824 42B Table 00-Modification from JESD209-4A (Contd) Itme # Subject Reference 8 1831.66 MR39 Register Information 60 http://members.jedecorgifile_upload/filegallery/download- document/index/document id/ 49876 29 1831.70 Read AC Timing 76 http://members.jedecorgifile_upload/filegallery/download ocument/index/document id/ 48780 30 1824.75A Write Timing 81-83https://vote.jedecorg/a_votingmachine/documents/ 311831.87 rite and Masked Write operation DQS 8893 ttps: //vote jedec. org/a votingmachine/documents ontrols(WDQs Control) RB16157-.pdf 32 18XXxx Masked Write Timing constraints 121-122 p: //members. jedec. org/file_ _ upload/filegallery/download document/index/document id/48256 33 1824.64 Masked Write Timing constraints 121-122 http://members.jedecorgifile_upload/filegallery/download document/index/document id/47293 341831.23Auto-precharGeOperation132-133https://vote.jedecorg/a_votingmachine/documents/ 35181932c Refresh command 140,143,http://members.jedec.org/file_upload/filegallery/download 146 ocument/index/document id/ 47852 3618×× Refresh Diagram 142 http://members.jedec.org/file_upload/filegallery/download document/index/document id/46630 37×X×× XX Refresh Requirement from SRX to SRE147-149 tp: /members. jedec. org/file upload/filegallery/download document/index/document id/50160 38 1831.95 Refresh Requirement 147-148 http:membersjedecorgifile_upload/filegallery/download- document/index/document id/ 51118 39×X×× XX Self Refresh Operation 149 http://members.jedec.orgifile_upload/filegallery/download document/index/document id/46570 40 1831.95 SELF REFRESH ABORT 152 Ittp: //members. jedec. org/file upload/filegallery/download- document/index/document id/51118 41 1819.52B MODE REGISTER READ(MRR 54 nttp: /members. jedec. org/file_upload/filegallery/download document/index/document id/46516 42183103 RR/MRW Timing Constraints: DQ ODT 160-167 htp. members. jedec. orgifile_uploadifilegallery/download- s Disable document/index/document id/50427 43181490A Command Bus Training 180-185https://votejedec.org/a_votingmachine/documents/ 44 1819.65B Frequency Set Point 186-187 http://membersjedec.orgifile_upload/filegallery/download document/index/document id/50144 45 1831.95 Frequency Set Point 186 http://membersjedecorgifile_upload/filegallery/download document/index/document id/51118 46183195 de Reister Write-WR Leveling mode 192http://members.jedec.org/file_upload/filegallery/download- n document/index/document_id/51118 47181995A Input Clock Frequency Stop and Change194 http://members.jedec.orgifile_upload/filegallery/download document/index/document id/46517 4811831.73 FIFO Write and Read Timing Diagram 203-206http://members.jedecorgifile_upload/filegallery/download- document/index/document id/48626 49×X×× xx Timing Constraints for Training 219 http:/members.jedec.org/file_upload/filegallery/download. Commands document/indexdocument id/50000 50 1831.95 Thermal Offset 220http://membersjedecorgifile_upload/filegallery/download document/index/document id/ 51118 51 1831.95 ZQ Calibration 223 http://members.jedec.orgifile_upload/filegallery/download document/index/document id/51118 52183195 lulti-chanNelConsiderationsforDual224http://members.jedecorg/file_upload/filegallery/download- Channel Devices document/index/document id/51118 53 1831.60A Non-target DRAM 238-242 http://members.jedecorg/file_upload/filegallery/download document/index/document id/49898 54XXx× XX Power-down 244 http://members.jedecorg/file_upload/filegallery/download- document/index/document id/50254 Page 3 of 310 LPDDR4 Specification Revision B tem1824.42B Table 00-Modification from JESD209-4A (Contd) Itme # Subject Reference 55×× X LPDDR4 VDDQ off during power down& 244 http://members.jedecorgifile_upload/filegallery/download- elf refresh with power down mode document/index/document id/46570 56 1819. 30 Input Clock Stop and Frequency Change 251-252 http://members.jedecorgifile_upload/filegallery/download ocument/index/document id/50802 571814.21ATruth Tables 253-254http:membersjedecorgifile_upload/filegallery/download- document/index/document id/48679 581819.61 Post Package Repair(PPR) 258-259 http://members.jedecorgifile_upload/filegallery/download- document/index/document id/46519 59 1824.26 Recommended DC Operating Conditions 261 http://members.jedecorg/file_upload/filegallery/download- document/index/document id/46551 60182403A 1. 1V High speed LVCMOS 65https://vote.jedec.org/a_votingmachine/documents/ 61 1831.22 Clock input definition 267-271 p //members. jedec. org/file_ upload/filegallery/download document/index/document id/46279 62 1831.22 DQS input definition 272-276 http:membersjedecorg/fileupload/filegallery/download- document/index/document id/45406 63 1831.95 DD Specifications http://members.jedecorg/file_upload/filegallery/download 294 document/index/document id/51118 641831.68 Clock Specification 295-206http://members.jedecorg/file_upload/filegallery/download- document/index/document id/49899 6518x× CA Timing Table 301 http:membersjedecorgifile_upload/filegallery/download- document/index/document id/48197 661824.42 Pata Timing 302310 http://members.jedecorg/file_upload/filegallery/downloac document/index/document id/48198 67××x× XX PBl timing parameter 30a tp: /Members. jedec. orgifile_upload/filegallery/down ad- document/index/document id/51125 68 1831.72 Symbol of dQ to DQ offset 307,310 http://membersjedecorgifileupload/filegallery/download- ocument/index/document id/48625 69 1824.73 DQS2DQ Rank to Rank 309,310https://vote.jedecorg/a_votingmachine/documents/ Page 4 of 310 Reference:http://members.jedecorg/fileupload/filegallery/download-document/index/documentid/51118 LPDDR4 Specification Revision B Item 1824 42B 1. Scope This document defines the LPDDR4 standard, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. The purpose of this specification is to define the minimum set of requirements for a JEdEC compliant 16 bit per channel sdram device with either one or two channels. LPDDR4 dual channel device density ranges from 4 Gb through 32 Gb and single channel density ranges from 2 Gb through 16 Gb. This document was created using aspects of the following standards: DDR2 (JESD79-2), DDR3JESD79-3), DDR4(JESD79-4), LPDDR(JESD209), LPDDR2 (JESD209-2)and LPDDR3 JESD209-3) Each aspect of the standard was considered and approved by committee ballot(s). The accumulation of these ballots was then incorporated to prepare the LPDDR4 standard Page 5 of 310 LPDDR4 Specification Revision B tem1824.42B 2. Package ballout& Pin Definition 2.1.1 Pad order for dual channel Ch A Top Ch B Top VDD2 VDD2 101 VDD2 41 VDD2 VSS 42 CKE A 102 VSS 142 CKE B VDD1 43 23456789 CS A 103 VDD1 143 CS B VDD2 44 VSS 104 VDD2 144 VSS VSS 45 CA1 A 1105 VSS 145 CA1 B VSSQ 46 CA0 A 106 VSSQ 146 CAO B DQ8 A 47 VDD2 107 DQ8 B 147 VDD2 VDDQ 48ODT(ca)A 108 VDDQ 148 ODT(ca)_B 9 DQ9 A VSS 109 DQ9 B 149VSS 10 VSSQ 50 VDD1 110 VSSQ 150 VDD1 1 DQ10_A 51 VSSQ 111DQ10B 151 VSSQ 12 VDDQ 52 DQ7 A 112 VDDQ 152 DQ7 B auo 13 DQ11A 53 VDDQ Top 113DQ11B 153 VDDQ 14 VSSQ 54 DQ6 A 114 VSSQ 154 DQ6 B 15 DQs1_tA55 VSSQ 115 DQS1 t B155 VSSQ 16 DQS1 CA 56 DQ5 A 116 DQS1CB156 DQ5 B 17 VDDQ 57 VDDQ 117 VDDQ 157 VDDQ 18DMI1 A 58 DQ4 A 118DMB158D04B 19 VSSQ 59 VSSQ 119 VSSQ 159 VSSQ 20 DQ12A 60 DMIO A 120DQ12B 160 DMIO B 21 VDDQ 61 VDDQ 121 VDDQ 161 VDDQ 22 DQ13 A 62 DQSO C A 122DQ13B 162 DQS0 C B 23 VSSQ 63 DSO t A 123 VSSQ 163 dSo t B 24 DQ14 A 64 VSSQ 124DQ14B 164 VSSQ 25 VDDQ 65 DQ3 A Bottom 125 VDDQ 165 DQ3 B 26 DQ15_A 66 VDDQ 126DQ15B 166 VDDQ 27 VSSQ 67 DQ2 A 127 VSSQ 167 DQ2 B 28 ZQ 128 RESET n168 VSSQ 29 VDDQ 69 DQ1 A 129 VDDQ 169 DQ1 B 30 VDD2 70 VDDQ 130 VDD2 170 VDDQ 31 VDD1 71 DQ0 A 131 VDD1 171 DQ0 B 32 VSS 72 VSSQ 32 VSS 172 VSSQ 33 CA5 A VSS 133 CA5 B 173 VSS 34 CA4 A 74 VDD2 134 CA4 B 174 VDD2 35 VDD2 75 VDD1 135 VDD2 175 VDD1 36 CA3 A 76 VSS 136 CA3 B 176 VSS 37 CA2 A VDD2 137 CA2 B 177 VDD2 38 VSS Ch A Bottom 1 138 VSS Ch B Bottom 39 C A 139 CK C B 40 CK t A 140cKtB」 Note 1. Applications are recommended to follow bit/byte assignments. Bit or Byte swapping at the application level requires review of MR and calibration features assigned to specific data bits/bytes 2. Additional pads are allowed for DRAM mfg-specific pads (dNU), or additional power pads as long as the extra pads are grouped with like-named pads Page 6 of 310 Reference:http://members.jedecorg/fileupload/filegallery/download-document/index/documentid/51118 LPDDR4 Specification Revision B Item 1824, 42B 2.1.2 Pad Order for single channel TOP VDD2 40 CK C VSS CK t VDD1 42 VDD2 23456789 VDD2 43 CKE VSS 44 VSSQ 45 VSS DQ8 46 CA1 VDDQ 47 CAO DQ9 48 VDD2 10 VSSQ 49 ODT(ca)1 DQ10 50 23 VDDQ 51VDD1 DQ11 52 VSSQ 14 VSSQ 53DQ7 15 DQS1t 54 VDDQ 16 DQS1 C 55 DQ6 VDDQ 56 VSSQ DM1 DQ5 19 VSSQ 58 VDDQ 20DQ12 59 DQ4 21 VDDQ 60 VSSQ 22 DQ13 DMIO 23 VSSQ VDDQ 24DQ14 63 DQS0 c 25 VDDQ 64 DSo t DQ15 VSSQ 27 VSSQ 66D03 28 ZQ 67 VDDQ 29 VDDQ 68 DQ2 30 VDD2 69 31 RESET n 70 DQ1 32 VDD1 71 VDDQ VSS DQO CA5 73 VSSQ CA4 36 VDD2 75 VDD2 37 CA3 76 VDD1 38 CA2 77 VSS 39 VSS 78 VDD2 Bottom Note 1. Applications are recommended to follow bit/byte assignments. Bit or Byte swapping at the application level requires review of MR and calibration features assigned to specific data bits/bytes 2. Additional pads are allowed for DRAM mfg-specific pads (DNU), or additional power pads as long as the extra pads are grouped with like-named pads 3. A RESET n pad is added. The ResET n pad location is vendor specific. See vendor device datasheets for details about RESET n pad location Page 7 of 310 PROPOSED 2.2.1 272-ball 15mm x 15mm 0. 4mm pitch, Quad-Channel PoP FBGA(top view) Using Variation VFFCDB for MO-273 DNU VSs VDE1 CAA_a VDDC a VDCQ DQ15 a DQ 13 1-8 VDDQ DQ81c-al VDDQ DQ10-_a DQ8_e D20_c DD1 DC2_c VDDa Daso-c-d voDa Do4-c DQ5 c DO7-c VDDQ CAO-c VDDQ CS1_c VD DNU D9道 ssDQt_c VssDQ3_c vss DOso CA2aGX。a K上Uc CK a Ck t c VSSCKc CKF CSo a Cola 刀巴<0 CA1 a VSS CAC a ODTca zQ0_c ZQ1_c Do6_avSS CK.tCK.c VSsDO14-c Da12_cDa13-c DNU, Nc Do. a Dos t Das c Das1 t c DQ11c RESET_n,ZQ,ODT ca DOo Note w Doo_b VD 1.15mm x 15mm, 0. 4mm ball pitch DQ8 DO1_bOSS 2 272 ball count 36 rows vss DQ9 d VDDQ DQ2 b 3. Top View, Al in top left corner Ab DQ_b Dasc_ 4. ODT ca_ [x] balls are wired to Odt(ca)[x] pads of Rank O dRAM die. OdT(ca)x] pads for other ranks cQS1tc Do11_d AC DaSo c b VSS (if present are disabled in the package vss Dos.d DMI1-aVDDo 5. Package requires dual channel die or functional equivalent of single channel die-stack. Channel a and DQs_b Dob 0Q12 d DC13 d Channel c shall be assigned to die channel a of different dram die VSS VSS Do14 d 6. Die pad Vss and vssq signals are combined to Vss package balls Do15 dVDDo AH CAC b ODTca b AJ CAlb VSS CA5 d CAA d CKE1 CSC CA2_d Ca3_d AM C<_b VSS CK c d CA2 b CKEO CKE1 d b vSs Do9_b ss DC4_d DTca_d Vss DQ12 b VDDQ DQs1 soo8bD。od 1DC2 d VDDo vODQCA0vDDa cs1_d voo: vss Reference:http://members.jedecorg/fileupload/filegallery/download-document/index/documentid/51118 Reference:http://members.jedecorg/fileupload/filegallery/download-document/index/documentid/51118 LPDDR4 Specification Revision B Item 1824, 42B 2.2.2 200-ball x 32 Discrete Package, 0.80mm x 0.65mm using Mo-311 0. 80mm Pitch 2 5 7 12 DNU VSS VDD2 ZQ1 VDD2 VSS DNU DNU B DNU DQ0 A VDDQ DQ7 VDDQ VDDQ DQ15 A VDDQ DQ8 ADNU VSS DQ1 A DMIO A DQ6 A VSS DQ14 A DMI1 A DQ9 A VSS D VDDQ VSS DQSo-_t A VSS VDDQ VDDQ VSS DQS1_t A VSS VDDQ E VSS DQ2 A DQSO C A DQ5A VSS VSS DQ13 A DQS1 C A DQ10 A VSS F VDD1 DQ3 A VDDQ DQ4 A VDD2 VDD2 DQ12 A VDDQ DQ11 A VDD1 VSs ODT_CA VSS VDD1 VDD1 VSS ZO VSS H VDD2 CAO_A CS1_A CSo VDD2 VDD2 CA2_A CA3_A CA4_AVDD2 J VSS CA1_A VSS CKEO-A CKE1_A CK_t_A CK_C_A VSS CA5_A VSS K VDD2 VSS VDD2 VSS CKE2 VSS VDD2 N VDD2 VSS VDD2 VSS CS2 B CKE2_B VSS VDD2 VSS VDD2 VSS CA1 B VSS CKEO BCKE1B CK t B CK C B VSS CA5 B VSS R VDD2 CAO B CS1 B CS0 B VDD2 VDD2 CA2 B CA3 B CA4 B VDD2 VSs ODT CA VDD1 VSS VSS VDD1 B ss VSS RESET_NVSS U VDD1 DQ3 B VDDQ DQ4B VDD2 VDD2 DQ12 B VDDQ DQ11 B VDD1 VSS DQ2_B DQS0 C B DQ5 B VSS VSS DQ13BDQS1 C B DQ10BVSS W VDDQ VSs DQSo-tB VSS VDDQ VDDQ VSS DQS1_t B VSS VDDQ VSS DQ1 B DMIO B DQ6 B VSS VSS DQ14 B DMI1 B DQ9 B VSS AA DNU DQ0_B VDDQ DQ7_B VDDQ VDDQ DQ15 B VDDQ DQ8B DNU AB DNU DNU VSS VDD2 VSS VSS VDD2 VSS DNU DNU Notes: 1.0.8mm pitch(X-axis), 0.65mm pitch(Y-axis), 22 rows 2. Top View, Al in top left corner 3. ODT CA [x balls are wired to Odt Ca)[x] pads of rank o draM die. ODT(ca)[x pads for other ranks (if present)are disabled in the package Page 9 of 310 Reference:http://members.jedecorg/fileupload/filegallery/download-document/index/documentid/51118 LPDDR4 Specification Revision B tem1824.42B 4. ZQ2, CKE2 A, CKE2 B, CS2 A, and CS2 B balls are reserved for 3-rank package For 1-rank and 2-rank package those balls are NC 5. Package requires dual channel die or functional equivalent of single channel die-stack. Die pad Vss and V signals are combined to Vss package balls 口u0oao Page 10 of 310

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