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BL24C256超高性价比EEPOM,SOIC8,TSSOP8两种封装都有。-BL24C256A.PDF
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详细说明：BL24C256超高性价比EEPOM,SOIC8,TSSOP8两种封装都有。-BL24C256A.PDF上海贝睑
BL24C256A256 Kbits(32768×8)
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WRITE PROTECT (WP): The bL24C256A has a Write Protect pin that provides hardware data protection
The Write Protect pin allows normal read /write operations when connected to ground(GND). When
the Write Protection pin is connected to Vcc, the write protection feature is enabled and operates as
shown in the following table 2
WP Pin Status
BL24C256A
At VCC
Full(256Array
At gnd
Normal Read/Write Operations
Functional Description
1. Memory Organization
BL24C256A, 256K SERIAL EEPROM: Internally organized with 256 pages of 64 bytes each, the 256K
requires a 15-bit data word address for random word addressing
2. Device Operation
CLOCK and DATA TRANSITIONS: The SDa pin is normally pulled high with an external device Data on the
SDA pin may change only during SCL low time periods (see Figure 2). Data changes during SCL high
periods will indicate a start or stop condition as defined below
START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which must
precede any other command (see Figure 3)
STOP CONDITION: A low-to-high transition of SDa with SCL high is a stop condition. After a read
sequence, the stop command will place the EEPROM in a standby power mode(see Figure 3)
ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the EEPROM in 8-bit
words. The EEPROM sends a"0"to acknowledge that it has received each word. This happens during
the ninth clock cycle
STANDBY MODE: The bL24C256A features a low-power standby mode which is enabled: (a)upon power-
up and(b) after the receipt of the stop bit and the completion of any internal operations
MEMORY RESET: After an interruption in protocol, power loss or system reset, any two-wire part can be
reset by following these steps
1. Clock up to 9 cycles
2. Look for sda high in each cycle while scl is high
3. Create a start condition
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Figure 2. Data Validity
DATA STABLE
DATA CHANGE DATA STABLE
Figure 3. Start and Stop Definition
SDA
SCL
START
STOP
Figure 4. Output Acknowledge
DATA IN
DATA OUT
START
ACKNOWLEDGE
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3. Device Addressing
The 256K EEPROM devices all require an 8-bit device address word following a start condition to enable
the chip for a read or write operation (see Figure 5)
The device address word consists of a mandatory 1,0 sequence for the first four most significant
bits as shown this is common to all the serial eeprom devices
The 256K EEPROM uses A2, al and ao device address bits to allow as much as eight devices on the
same bus. These 3 bits must be compared to their corresponding hardwired input pins. the a2, al and
A0 pins use an internal proprietary circuit that biases them to a logic low condition if the pins are
allowed to float
The eighth bit of the device address is the read /write operation select bit. a read operation is initiated if
this bit is high and a write operation is initiated if this bit is low
Upon a compare of the device address, the EEPROm will output a 0". If a compare is not made, the
chip will return to a standby state
DATA SECURITY: The bl240256a has a hardware data protection scheme that allows the user to write
protect the entire memory when the wp pin is at vco
4. Write Operations
BYTE WRITE: A write operation requires an 8-bit data word address following the device address word
and acknowledgment. Upon receipt of this address, the EEProM will again respond with a 0"and then
clock in the first 8-bit data word. Following receipt of the 8-bit data word, the EEPROM will output a"0
and the addressing device, such as a microcontroller, must terminate the write sequence with a stop
condition. At this time the EEProm enters an internally timed write cycle, tWR, to the nonvolatile
memory. All inputs are disabled during this write cycle and the eeprom will not respond until the write
is complete(see Figure 6)
PAGE WRITE: A write operation requires an 8-bit data word address following the device address word
and acknowledgment. Upon receipt of this address, the EEPROM will again respond with a"0"and then
clock in the first 8-bit data word. Following receipt of the 8-bit data word, the EEPRoM will output a 0
and the addressing device, such as a microcontroller, must terminate the write sequence with a stop
condition. At this time the eeprom enters an internally timed write cycle, tWr, to the nonvolatile
memory. All inputs are disabled during this write cycle and the EEPROM will not respond until the write
is complete(see Figure 7)
The data word address lower five bits are internally incremented following the receipt of each data
word. The higher data word address bits are not incremented, retaining the memory page row location
When the word address, internally generated, reaches the page boundary, the following byte is placed
at the beginning of the same page. If more than 64 data words are transmitted to the EEProm, the
data word address will"roll over"and previous data will be overwritten
WRITE IDENTIFICATION PAGE: The Identification Page (64 bytes)is an additional page which can be
written and (later) permanently locked in Read-only mode. It is written by issuing the Write
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Identification Page instruction. This instruction uses the same protocol and format as Page Write(into
memory array), except for the following differences
Device type identifier= 1011b
MSB address bits B15/B6 are don't care except for address bit b10 which must be"0
LSB address bits b5/b0 define the byte address inside the Identification page
If the Identification page is locked, the data bytes transferred during the Write Identification Page
instruction are not acknowledged(NoAck
ACKNOWLEDGE POLLING: Once the internally timed write cycle has started and the EEPROM inputs are
disabled, acknowledge polling can be initiated. This involves sending a start condition followed by the
device address word. The read /write bit is representative of the operation desired. Only if the internal
write cycle has completed will the EEPROM respond with a 0 allowing the read or write sequence to
continue
5. Read Operations
Read operations are initiated the same way as write operations with the exception that the read/write
select bit in the device address word is set to " 1". there are three read operations: current address read
random address read and sequential read
CURRENT ADDRESS READ:
The internal data word address counter maintains the last address accessed during the last read or
write operation, incremented by one. This address stays valid between operations as long as the chip
power is maintained. The address"roll over"during read is from the last byte of the last memory page
to the first byte of the first page. The address"roll over" during write is from the last byte of the current
page to the first byte of the same page. Once the device address with the read /write select bit set to
1 is clocked in and acknowledged by the EEPROM, the current address data word is serially clocked
out. the microcontroller does not respond with an input "0" but does generate a following stop
condition (see Figure 8)
RANDOM READ
A random read requires a"dummy" byte write sequence to load in the data word address. Once the
device address word and data word address are clocked in and acknowledged by the EEPROM, the
microcontroller must generate another start condition. The microcontroller now initiates a current
address read by sending a device address with the read/write select bit high. The EEPROM
acknowledges the device address and serially clocks out the data word. The microcontroller does not
respond with a"0"but does generate a following stop condition(see Figure 9)
SEQUENTIAL READ: Sequential reads are initiated by either a current address read or a random address
read After the microcontroller receives a data word, it responds with an acknowledge. As long as the
EEPROM receives an acknowledge, it will continue to increment the data word address and serially
clock out sequential data words. When the memory address limit is reached, the data word address will
roll over"and the sequential read will continue. The sequential read operation is terminated when the
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microcontroller does not respond with a"0"but does generate a following stop condition(see Figure
10)
READ IDENTIFICATION PAGE: The Identification Page (64 bytes) is an additional page which can be
written and (later) permanently locked in Read-only mode
The Identification Page can be read by issuing an Read Identification Page instruction. This instruction
uses the same protocol and format as the random Address read (from memory array) with device type
identifier defined as 1011b. the msb address bits b15/b6 are don ' t care the lsb address bits b5/b0
define the byte address inside the Identification Page. The number of bytes to read in the id page must
not exceed the page boundary (e.g. when reading the Identification Page from location 10d, the
number of bytes should be less than or equal to 22, as the ID page boundary is 64 bytes)
LOCK IDENTIFICATION PAGE: The Lock Identification Page instruction(Lock ID) permanently locks the
Identification page in Read-only mode. The Lock ID instruction is similar to Byte Write(into memory
array) with the following specific conditions
Device type identifier 1011b
Address bit b10 must be 1, all other address bits are don 't care
The data byte must be equal to the binary value xxxx xxix, where x is don't care
Table 3. FIRST WORD ADDRESS
BIs
B14
B13
B12
B
B10
B9
B8
Table 4, SECOND WORD ADDRESS
B7
B6
BS
B4
B3
B2
BI
BO
Figure 5. Device Address
MSB
LSB
a2
A1
AO
R/W
Figure 6. Byte Write
T
DEVICE FIRST WORD
ADDRESS
SECOND WORD
T
ADDRESS
ADDRESS
DATA
E
SDA
LINE
BWK
Note1*=DON'T'T CARE bits
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Figure 7. Page Write
TAR
DEVICE
DDRESs I
FIRST WORD
SECOND WORD
T
ADDRESS
ADDRESS
DATA(n
DATA(n+l)
DATA(n+1)
sTo
LINE
lLLlLl
LRA
S C
BWK
AcK
Note I*=DON'T CARE bits
Figure 8. Current Address Read
R
A DEVICE E
T
R
ADDRE
DATA
SDA
LINE
LRA
ACK
BWK
Figure 9. Random Read
R
R
A DEVICE
Ist. 2nd wOrD
A DEVICE
T
DDRESS
ADDRESS
R ADDRESS
DATA(n)
SDA
LINE
L A
S/ C
S C
ACK
B
BWK
B K
DUMMY WRITE
Note1*=DONT CARE hit
Figure 10. Sequential Read
R
DEVICE
E
T
ADDRESS
DATA(n)
DATA(n+I)
DATA(n+2)
DATA(n+x
LINE
R A
K
ACK
WK
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Electrical Characteristics
Absolute Maximum Stress ratings
DC Supply Voltage.........0.3V to+6.5V
Input /Output Voltage.... GND-03V to VCC+0.3v
Operating Ambient Temperature
40Cto+85°
Storage Temperature.∴-65℃Cto+150°C
Electrostatic pulse(Human Body model)... 8000V
Comments
Stresses above those listed under "Absolute Maximum Ratings"may cause permanent damage to this
device. These are stress ratings only. Functional operation of this device at these or any other
conditions above those indicated in the operational sections of this specification is not implied or
intended. Exposure to the absolute maximum rating conditions for extended periods may affect device
reliabi
DC Electrical characteristics
Applicable over recommended operating range from ta =-40 c to+85C, Vcc =+1.7V to +5.5V
(unless otherwise noted)
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Parameter
Symbol Min
Max Ur
Condition
Supply voltage
Vccl
Supply voltage
2.5
5.5
upply Voltage
2.7
5.5
V
Supply voltage
4.5
5.5
V
Supply current VCC=5.0V
0.4
1.0
mA
REAd at 400KHZ
Supply Current VCC=5.0V
Icc?
2.0
A
WritE at 400KHZ
Supply Current VCC=1.7v
IsBi
0.6
1.0
VINVcc or Vss
Supply Current VCC=2.5V
Is
1.0
2.0
A
VnN= Vcc orⅤ
Supply Current VCc-27V
Isp
1.0
2.0
A
VIN-Vcc or Vss
Supply current vcc=5.0v
2.0
5.0
A
VINVCc orⅤss
Input Leakage current
0.10
3.0
LA
VIN=Vcc or Vss
Output Leakage Current
0053.0
A
Vour= Vcc orⅤss
Input Low leve
-0.3
Vcc×0.3
Vccl 8V to 5.5v
Input High Level
VmVc×0.7
Vcc+0.3 V
Vccl 8V to 5,5v
Input Low leve
VI2
-0.3
Vc×0.2V
VCc=1.7V
Input High Level
VcC×0.7
Vac+0.3V
Ⅴc-1.7V
Output low level vcc-50v
0.4
V
IoL-3. 0mA
Output Low Level VCC=3.0V
VoL
0.4
V
IoL=.ImA
Output Low Level VCC=1.7V
0.2
loL=0.15mA
Pin Capacitance
Applicable over recommended operating range from ta= 25C, f= 1.0 MHz, VCC =+1.7V
Parameter
Symbol Min Typ Max Unit Condition
Input/Output Capacitance SDa)
/0
Ⅵ1o=0
Input Capacitance(A0, A1 A2, SCL) CIN.
6
VIN=OV
AC Electrical Characteristics
Applicable over recommended operating range from ta=-40C to +85C, VCC =+1.7V to +5.5V, CL
1 TTL Gate and 100 pF(unless otherwise noted
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