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详细说明：AD8065 datasheet，很难找，官方资料。AD8065 datasheet，很难找，官方资料。AD8065 datasheet，很难找，官方资料。AD8065/AD8066
SPECIFICATIONS
TA=25C, Vs=+5V, RL= 1 kn, unless otherwise noted
Table 1
Parameter
Conditions
Min
Typ
Max Unit
DYNAMIC PERFORMANCE
3 dB Bandwidth
G=+1,Vo=02Vpp(AD8065)
100
145
MHz
G=+1,vo=0.2Vpp(AD8066)
120
MHZ
G=+2, Vo=0.2V p-p
G=+2, Vo=2Vp-p
42
MH
Bandwidth for o1 db flatness
G=+2, Vo=0.2V p-p
MHZ
Input Overdrive Recovery Time
G=+1,-55Vto+55V
175
Output Recovery Time
G=-1,-5.5Vto+55V
170
Slew ra
G=+2,Vo=4∨Step
130
80
Settling Time to O1%
G=+2, Vo=2VStep
55
G=+2, Vo=8VStep
205
NOISE/HARMONIC PERFORMANCE
SFDR
fc=1 MHz, G=+2, Vo=2V p-p
88
dBc
fc=5 MHZ, G=+2, Vo=2V p-p
67
dBc
fc-1 MHz, G=+2, vo=8V p-p
dBc
Third-Order Intercept
fc=10 MHz, RL=100 Q
24
dBm
Input voltage noise
f= 10 kHz
nV//Hz
nput Current Noise
f= 10 khz
06
Differential gain error
NTSC, G=+2, Rl=150Q
0.02
%
Differential phase error
NTSC,G=+2 RL=150Q
002
Degree
DC PERFORMANCE
nput Offset Voltage
∨cM=0V,SO| PAckage
04
5
m
Input Offset Voltage Drift
nput Bias Current
SOIC Package
122
μV/°C
A
Input Offset Current
10
A
Open-Loop gain
Vo=±3VRL=1k
100
113
dB
INPUT CHARACTERISTICS
Common-Mode Input Impedance
1000|2.1
GQ‖lpF
Differential Input Impedance
100045
GΩ‖lpF
Input Common-Mode voltage Range
FET Input Rang
5to+1.7
50to+2.4
Usable range
See the theory of operation section
50to+50
Common-Mode rejection ratio
VcM=-1V to+1 V
100
dB
VcM=-1V to+1 V(SOT-23)
82
dB
OUTPUT CHARACTERISTICS
Output Voltage Swing
RL= 1 kQ
4.88to+4.90-494to+4.95
RL=150 Q
4.8to+4.7
Output Current
Vo=9v p-p, SFDR>-60 dBc, f=500 kHz
35
A
Short-Circuit current
mA
Capacitive Load drive
30%Overshoot g=+1
20
pF
POWER SUPPLY
Operating Range
24
Quiescent Current per amplifier
7,2
m
Power Supply Rejection Ratio
士PSRR
100
dB
Rev. E Page 3
AD8065/AD8066
Q TA=25C, Vs=+12 V, RL=1 kQ, unless otherwise noted
Table 2
Parameter
Conditions
Min
Ty
Max Unit
DYNAMIC PERFORMANCE
MHz
.3 db Bandwidth
G=+1,Vo=02Vpp(AD8065)
100
145
MHZ
G=+1, Vo=0.2V p-p(AD8066
100
115
MHZ
G=+2, Vo=0.2V p-p
G=+2, Vo=2Vp-p
Bandwidth for o1 db flatness
G=+2, Vo=0.2V p-p
Input Overdrive recovery
G=+1,-125Vto+125V
175
Output Overdrive Recovery
G=-1,-12.5Vto+125V
170
Slew rate
G=+2, Vo=4VStep
130
180
Settling time to o1%
G=+2, Vo=2 VStep
55
2,vo=10∨step
250
ns
NOISE/HARMONIC PERFORMANCE
SFDR
fc= 1 MHz, G=+2, Vo=2V p-p
-100
dBc
fc=5 MHz,G=+2, Vo=2V p-p
dBc
fc=1 MHz, G=+2, Vo=10 V p-p
dBc
Third-Order Intercept
f=10MHzR1=100Ω
24
dBm
Input Voltage Noise
7
nV/vHz
Input Current noise
f= 10 khz
fA/VH
Differential gain error
NTSC, G=+2, RL= 150 Q
0.04
%
Differential phase error
NTSC, G=+2, RL=150Q
003
Degree
DC PERFORMANCE
nput Offset Voltage
VcM=0V, SOIC Package
0.4
1.5
Input Offset Voltage Drift
17
V°C
Input Bias Current
SOIC Package
25
Input Offset Current
10
2
A
Open-Loop Gain
Vo=±10VRL=1kQ
103
114
INPUT CHARACTERISTICS
Common-Mode input Impedance
1000|121
GΩ‖pF
Differential Input Impedance
10004.5
GΩ‖pF
Input Common-Mode Voltage Range
FET Input range
12to+8.5
120to+9.5
Usable range
See the Theory of Operation section
120to+12.0
Common-Mode Rejection Ratio
VcM=-1Vto+1V
100
dB
VcM=-1V to+1 V(SOT-23)
91
dB
OUTPUT CHARACTERISTICS
Output Voltage Swing
RL=1 ko
118to+118-119to+11.9
RL= 350 Q
11.25to+11.5
Output Current
Vo=22V p-p SFDR 2-60 dBc, f=500 kHz
30
mA
Short-Circuit Current
120
A
Capacitive load drive
30% Overshoot g=+1
25
OF
POWER SUPPLY
Operating range
24
Quiescent Current per amplifier
6.6
7.4 mA
Power Supply Rejection Ratio
±PSRR
84
93
dB
Rev. E Page 4 of 28
AD8065/AD8066
TA=25C, Vs=5V, RL=l ko, unless otherwise noted
Table 3
Parameter
Conditions
Min
Tv
Max Unit
DYNAMIC PERFORMANCE
3 db Bandwidth
G=+1,Vo=0.2Vp-p(AD8065
125
155
MHZ
G=+1,Vo=0.2Vpp(AD8066)
110
130
G=+2, Vo=0.2Vp-p
50
G=+2, Vo=2Vp-p
Bandwidth for 0.1 db flatness
G=+2, Vo=0.2Vp-p
Input Overdrive Recovery Time
G=+1,-05Vto+55V
175
Output Recovery Time
G=-1,-0.5Vto+5.5V
170
Slew rate
G=+2, Vo=2VStep
105
160
Settling Time to.1%
G=+2, Vo=2VStep
60
ns
NOISE/HARMONIC PERFORMANCE
SFDR
fc=1 MHz, G=+2, Vo=2V p-p
65
dBc
fc=5 MHz, G=+2, Vo=2v p-p
50
dBc
Third-Order Intercept
f=10MHz,RL=1009
22
dB
Input voltage noise
f= 10 khz
7
nV/vhz
Input Current noise
f= 10 kHz
0.6
fA//Hz
Differential gain Error
NTSC,G=+2, RL-150 Q
0.13
%
Differential phase error
NTSC,G=+2, RL=150Q
0.16
Degree
DC PERFORMANCE
nput Offset Voltage
VcM=1.0 V, SOIC Package
0.4
1.5 mV
Input offset Voltage drift
17 HV/oc
Input bias current
SOIC Package
p
TMIN to TN
25
nput Offset Current
p
TMiN to Tmax
O
en-Loo
p
lo=1V to 4 V(AD8065)
100
113
Vo=1 to 4 V (AD8066
103
dB
INPUT CHARACTERISTICS
Common -Mode Input Impedance
10002.1
GΩ‖pF
Differential Input Impedance
100045
GQ‖pF
Input Common-Mode voltage Range
FET Input Range
0to1.7
0to24
Usable range
See the Theory of operation section
0to5.0
Common - Mode rejection ratio
Vcm=1Vto 4V
74
100
dB
Ve=1 V to 2V(SOT-23)
78
91
dB
OUTPUT CHARACTERISTICS
Output Voltage Swing
RL=1kQ
0.1to4850.03to495
RL=1509
0.07to483
Output Current
Vo=4Vp-p, SFDR2-60 dBC, f= 500 kHz
35
Short-Circuit current
75
A
Capacitive Load Drive
30%○ vershoot g=+1
POWER SUPPLY
Operating rane
24
Quiescent Current per Amplifier
5.8
6.4
7.0mA
Power Supply Rejection Ratio
±PSRR
-78
100
Rev. E Page 5
AD8065/AD8066
ABSOLUTE MAXIMUM RATINGS
Table 4
Parameter
Rating
Stresses above those listed under absolute Maximum ratings
Supply Voltage
26.4V
may cause permanent damage to the device This is a stress
Power Dissipation
See Figure 3
rating only; functional operation of the device at these or any
Common-Mode Input Voltage
VEE-0.5V to Vcc+0.5V
other conditions above those indicated in the operational
Differential Input voltage
1.8V
section of this specification is not implied. Exposure to absolute
Storage Temperature
65°Cto+125°C
maximum rating conditions for extended periods may affect
Operating Temperature Range
40°Cto+85C
device reliability
Lead Temperature Range
300C
(Soldering 10 sec)
ESD CAUTION
ESD(electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection although this product featur
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high enerdr
WARNINGE
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
ESD SENSITIVE DEVICE
degradation or loss of functionality
Rev. E Page 6 of 28
AD8065/AD8066
MAXIMUM POWER DISSIPATION
The maximum safe power dissipation in the AD8065/AD8066
packages is limited by the associated rise in junction
temperature(T) )on the die. The plastic encapsulating the d
will locally reach the junction temperature. At approximately
150C, which is the glass transition temperature the plastic will
change its properties. Even temporarily exceeding this
temperature limit can change the stresses that the package
exerts on the die, permanently shifting the parametric
performance of the AD8065/AD8066 Exceeding a junction
temperature of 175C for an extended period of time can result
n changes in the silicon devices, potentially causing failure
The still-air thermal properties of the package and PCB(ajA
ambient temperature(TA), and total power dissipated in the
package(Pd) determine the junction temperature of the die. The
junction temperature can be calculated as
igure 3. Maximum Power Dissipation Vs Temperature for a 4-Layer Board
T=Tn+(P×日1
Airflow will increase heat dissipation, effectively reducing eJA.
Also, more metal directly in contact with the package leads
The power dissipated in the package(PD)is the sum of the
from metal traces, through holes, ground, and power planes will
quiescent power dissipation and the power dissipated in the
reduce the bjA. Care must be taken to minimize parasitic
package due to the load drive for all outputs. The quiescent
capacitances at the input leads of high speed op amps as
power is the voltage between the supply pins(Vs)times the
discussed in the Layout, Grounding, and Bypassing
quiescent current(Is). Assuming the load (ri)is referenced to
Considerations section
midsupply, then the total drive power is Vs/2 X TouT, some of
Figure 3 shows the maximum safe power dissipation in the
which is dissipated in the package and some in the load(vourx
package versus the ambient temperature for the soic
lour). The difference between the total drive power and the load
(125C/W), SOT-23(180%C/W), and MSOP(150C/W)
power is the drive power dissipated in the package
packages on a JEDEC standard 4-layer board. OJA values are
Pp=Quiescent Power+( Total Drive Power-Load Power
approximations
OUTPUT SHORT CIRCUIT
PD=(vs xIs )+(Vsx Your)-vour2
Shorting the output to ground or drawing excessive current for
R
R
the ad8065/AD8066 will likely cause catastrophic failure
RMS output voltages should be considered If RL is referenced to
Vs-, as in single-supply operation, then the total drive power is
Vs×Ior.
If the rms signal levels are indeterminate then consider the
worst case, when Vour= Vs/4 for Ri to midsupply
V
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