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详细说明：UTMI+ Low Pin Interface (ULPI) 接口文档，指导调试硬件USB接口，传输时序图很清晰明了，可以用于调试单片机和USB3300或FPGA和USB3300，等使用ULPI接口的芯片UTMI+ Low Pin Interface Specification, Revision 1.1
October 20. 2004
Promoters
ARC International Inc
Conexant systems, Inc
Mentor Graphics corporation
Philips
SMSC
Trans Dimension Inc
Contributors
Bart vertentes
Philips
Batuhan okur
Philips
Bill Anderson
Motorola
Bill McInerney
Trans Dimension
Brian booker
Cypress
Chris Belanger
ARC
Chris Kolb
ARC
Chris schell
Philips
Chung Wing Yan
Daye Sroka
Philips
David Wang
Philips
David wooten
TransDimension
Eric Kawamoto
SMSC
Farran Mackay
Philips
frank frazier
Conexant
Fred roberts
Synopsys
Hassan farooq
Conexant
Hyun Lee
Trans Dimension
lan parr
Mentor
Jay standiford
Trans Dimension
Jerome Tjia
Philips
Mark Saunders
Mentor
Mohamed benromdhane Conexant
Morgan monks
SMSC
Nabil takla
Peter Tengstrand
ARC
Ramanand mandayam
Conexant
Rob Douglas
Mentor
Saleem mohamed
Synopsys
Shaun reemeyer
Philips(author)
Simon Nguyen
Cypress
Subramanyam sankaran philips
Sue Vining
Texas Instruments
Terry remple
Timothy Chen
Conexant
Vincent Chang
Conexant
Questions should be emailed to lpcwgboardrooms.org
UTMI+ Low Pin Interface Specification, Revision 1.1
October 20. 2004
Table of contents
Introduction
1.1 Genera
1.2 Naming convention
1.3 Acronyms and I erms…………
11111
1.4 References
2. Generic Low Pin Interface
2.1 General
2.2 Signals
2.3 Protocol
2.3.1 Bus Ownership
23.2 Transferring data……
2.3.3 Aborting data
3. UTMI+ Low Pin Interface
3.1 General
3.2 Signals
2333455679
3.3 Block Diagram
3.4 Modes
3.5 Power on and reset
10
3.6 Interrupt Event Notification
10
3.7 Timing
3.7.1c|ock
3.7.2 Control and data
13
3.8 Synchronous Mode
5
3.8.1 ULPI Command Bytes
15
3.82 USB Packets
8
3.8.3 Register Operations
30
3.8.4 Aborting ULPI Transfers
37
3.8.5 USB Operations
3.8.6 Vbus Power Control (internal and external)
52
3.8.7 OTG Operations
52
3.9 Low Power Mode
55
3.9.1 Data line definition for low power mode
55
3.9.2 Entering Low Power Mode
55
3.9.3 EXiting Low Power Mode
56
3.9.4 False Resume rejection
57
3. 10 Full Speed /Low Speed Serial Mode(Optional)
58
3.10.1 Data line definition for fsls serialMode
58
3.10.2 Entering FsLsSerialMode
59
3.10.3 EXiting FSLs SerialMode
60
3.11 Carkit Mode(Optional)
61
3. 12 Safeguarding PHY Input Signals
62
4. Registers
65
4.1 Register Map
4.2 Immediate Register Set
67
4.2.1 Vendor id and product id
67
4.2.2 Function control
68
4.2.3 Interface control
69
4.2.4 OTG Control
42.5 USB Interrupt Enable Rising……
72
4.2.6 USB Interrupt enable falling
.73
2.7 USB Interrupt Statu
74
4.2.8 USB Interrupt Latch
75
4.2.9 Debug
76
4.2.10 Scratch Register
76
4.2.11 Carkit Control
77
4.2. 12 Carkit Interrupt Delay
77
UTMI+ Low Pin Interface Specification, Revision 1.1
October 20. 2004
4.2.13 Carkit Interrupt Enable
78
4.2.14 Carkit Interrupt Status
78
4.2. 15 Carkit Interrupt Latch
79
4.2.16 Carkit Pulse Control……………
4.217 Transmit positive width
80
4.2. 18 Transmit Negative Width
80
4.2.19 Receive Polarity Recovery
80
4.2.20 Reserved
81
4.2.21 Access Extended register set
81
4.2.22 Vendor-specific
81
4.3 Extended Register Set
81
4.4 Register Settings for all Upstream and Downstream signalling modes
81
5. t&MT Connector
83
5.2 Daughter-card(UUT) Specification
5.1 Genel
83
83
UTMI+ Low Pin Interface Specification, Revision 1.1
October 20. 2004
Figures
Figure 1-LPI generic data bus ownership
Figure 2-LPI generic data transmit followed by data receive
Figure 3-Link asserts stp to halt receive data
Figure 4- Creating a ULPI system using wrappers
33457
Figure5- Block diagram of ULPI PHY…………
Figure 6-Jitter measurement planes
Figure 7-ULPI timing diagram
13
Figure 8- Clocking of 4-bit data interface compared to 8-bit interface
Figure 9- Sending of RX CMD
Figure 10-USB data transmit (NOPID)
Figure 11-USB data transmit (PID)
19
Figure 12 -PHY drives an RX CMD to indicate EOP(FS/LS Line State timing not to scale).....20
Figure 13-Forcing a full/low speed USB transmit error(timing not to scale
21
Figure 14 -USB receive while dir was previously low
Figure 15-USB receive while dir was previously high
Figure 16-USB receive error detected mid-packet
Figure 17-USB receive error during the last byte
Figure 18-USB HS, FS, and ls bit lengths with respect to clock
26
Figure 19-HS transmit-to-transmit packet timing
29
Figure 20- HS receive-to-transmit packet timing
29
Figure 21- Register write
30
Figure 22- Register read
31
Figure 23 -Register read or write aborted by UsB receive during TX CMd byte
31
Figure 24-Register read turnaround cycle or Register write data cycle aborted by USB receive.... 32
Figure 25-USB receive in same cycle as register read data. USB receive is delayed
33
Figure 26- Register read followed immediately by a USB receive
∴33
Figure 27- Register write followed immediately by a USB receive during stp assertion
34
Figure 28- Register read followed by a USB receive
34
Figure 29-Extended register write
35
Figure 30-Extended register read
35
Figure 31- Extended register read aborted by USB receive during extended address cycle
Figure 32- PHY aborted by Link asserting stp Link performs register write or USB transmit ..
37
Figure 33- PhY aborted by Link asserting stp. Link performs register read
…38
Figure 34- Link aborts Phy link fails to drive a tX cmd. Phy re-asserts dir...............38
Figure 35- Hi-Speed Detection Handshake( Chirp) sequence(timing not to scale)..........40
Figure 36- Preamble sequence(D+/D-timing not to scale)......
41
Figure 37-LS Suspend and Resume(timing not to scale)
43
Figure 38-FS Suspend and Resume(timing not to scale)
∴44
Figure 39- HS Suspend and Resume(timing not to scale)
46
Figure40- Low Speed Remote Wake-υ Jp from Low Power Mode( (timing not to scale)…………………47
Figure41- Full Speed Remote Wake- Up from Low Power Mode( timing not to scale)……………….8
Figure 42-Hi-Speed Remote Wake-Up from Low Power Mode( timing not to scale)
49
Figure 43- Automatic resume signalling( timing not to scale)
50
Figure 44-USB packet transmit when OpMode is set to 11b
51
Figure 45-RX CMD VA VBUS VLD s Vbus indication source
∴54
Figure 46-Entering low power mode
Figure 47-Exiting low power mode when PHY provides output clock
Figure 48-Exiting low power mode when Link provides input clock
Figure 49- PHY stays in Low Power Mode when stp de-asserts before clock starts
57
Figure 50- PHY re-enters Low Power Mode when stp de-asserts before dir de-asserts
57
Figure 51- Interface behaviour when entering Serial Mode and clock is powered down
59
Figure 52- Interface behaviour when entering Serial Mode and clock remains powered. ........................59
Figure53- Interface behaviour when exiting serial Mode and clock is not running…………….60
Figure 54-Interface behaviour when exiting Serial Mode and clock is running
,60
Figure 55-PHY interface protected when the clock is running
62
Figure 56- Power up sequence when PHY powers up before the link Interface is protected ....................63
Figure 57- PHY automatically exits Low Power Mode with interface protected
63
Figure 58-Link resumes driving ULPI bus and asserts stp because clock is not running
64
UTMI+ Low Pin Interface Specification, Revision 1.1
October 20. 2004
Figure 59-Power up sequence when link powers up before PHY(ULPI 1.0 compliant links )......64
Figure 60- Recommended daughter-card configuration(not to scale)
83
UTMI+ Low Pin Interface Specification, Revision 1.1
October 20. 2004
Tables
Table 1-LPI generic interface signals
Table 2- PhY interface signals
6
Tabe3- Mode summary...…,…
Table 4-Clock timing parameters
T able 5-ULPl interface timing
13
Table 6-Transmit Command (TX CMD)byte format
15
Table 7-Receive Command(RX CMD)byte format
16
Table 8-USB specification inter-packet timings
T able 9- PhY pipeline delays
.27
Table 10- link decision times
28
Table 11-OTG Control Register power control bits
52
Table 12-vbus comparator thresholds
52
Table 13-RX cmd vbus valid over-current conditions
T able 14-Vbus indicators in the RX CMD required for typical applications
54
T able 15-Interface signal mapping during Low Power Mode.......
55
Table 16- Serial Mode signal mapping for 6-pin FsLs SerialMode
58
Table 17- Serial Mode signal mapping for 3-pin FsLsSerialMode...
..58
Table 18- Carkit signal mapping
61
Table 19- Register ma
66
Table 20-Register access legend
67
Table 21- Vendor ID and Product iD register description
67
Table 22- Function Control register
68
Table 23- Interface control register
Table 24-OTG Control register
Table 25-USB Interrupt Enable Rising register
72
Table 29-Rules for setting Interrupt Latch register bits
Table 26-USB Interrupt Enable Falling register
73
Table 27- USB Interrupt Status register
74
Tabe28- USB Interrupt Latch register……
75
75
Tabe30- Debug register………
76
Tab|e31- Scratch register……
L国E111面面
76
Table 32- Carkit Control register
Table 33- Carkit Interrupt Delay register
翻面
Tabe34- Carkit Interrupt Enable register……
78
Table 35- Carkit Interrupt status register
78
Table 36-Carkit Interrupt Latch register.
79
Table 37- Carkit Pulse Control
79
Table 38-Transmit positive width
80
Table 39- Transmit Negative width
国国面国面B面面
80
Table 40- Receive Polarity Recovery
81
Table 4 1-Upstream and downstream signalling modes
82
Table 42- T&MT connector pin view...
84
Table 43-T&MT connector pin allocation..
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Table 44-T&MT pin description
85
UTMI+ Low Pin Interface Specification, Revision 1.1
October 20. 2004
Introduction
General
This specification defines a generic PHY interface in Chapter 2
In Chapter 3, the generic interface is applied to the UTMI+ protocol, reducing the pin count for discrete USB
transceiver implementations supporting On-The-Go, host, and peripheral application spaces
12
Naming convention
Emphasis is placed on normal descriptive text using underlined Arial font, e.g. must
Signal names are represented using the lowercase bold Arial font, e. g clk
Registers are represented using initial caps, bold Arial font, e.g. OTG Control
Register bits are represented using initial caps, bold italic Arial font, e. g. USB Interrupt Enable Falling
1.3 Acronyms and terms
A-device
Device with a Standard-A or Mini-A plug inserted into its receptacle
B-device
Device with a Standard-B or Mini-B plug inserted into its receptacle
DRD
Dual-Role device
FPGA
Field Programmable Gate Array
Full Speed
HNP
Host Negotiation Protocol
Hi-Speed
Link
ASIC. SIE or fpga that connects to an ulpi transceiver
Low Pin Interface
Low Speed
OTG
On-The-Go
PHY
Physical Layer(Transceiver)
PLL
Phase Locked Loop
SEO
Single Ended Zero
SIE
Serial Interface Engine
SRP
Session Request Protocol
T&MT
Transceiver and macrocell tester
ULP
JTMI+ Low Pin Interface
USB
Universal serial bus
USB-F
USB Implementers Forum
UTMI
USB 2.0 Transceiver macrocell Interace
UUT
Unit Under test
References
[Ref 1] Universal Serial Bus Specification, Revision 2.0
[Ref 2] On-The-Go Supplement to the USB 2.0 Specification, Revision 1.0a
[Ref 3] UsB 2.0 Transceiver Macrocell Interface(UTMI) Specification, v1.05
[Ref 4] UTMI+ Specification, Revision 1.0
[Ref 5] CEa-2011, oTG Transceiver Specification
[Ref 6] CEA-936A, Mini-USB Analog Carkit Interface Specification
[Ref 7] UsB 2.0 Transceiver and Macrocell Tester (T&MT) Interface Specification, Version 1.2
UTMI+ Low Pin Interface Specification, Revision 1.1
October 20. 2004
2
Generic Low Pin Interface
2.1
General
This section describes a generic low pin interface( LPl)between a Link and a PhY Interface signals are
defined and the basic communication protocol is described. The generic interface can be used as a common
starting point for defining multiple application-specific interfaces
Chapter 3 defines the UTMI+ Low Pin Interface (ULPD), which is based on the generic interface described
here. For ULPI implementations, the definitions in chapter 3 over-ride anything defined in chapter 2
2.2
Signals
The LPI transceiver interface signals are described in Table 1. The interface described here is generic, and
can be used to transport many different data types. Depending on the application, the data stream can be
used to transmit and receive packets, access a register set, generate interrupts, and even redefine the
interface itself. All interface signals are synchronous when clock is toggling and asynchronous when clock
is not toggling. Data stream definition is application-specific and should be explicitly defined for each
application space for inter-operability
bus. If required, an implementation can define the Link as the master. if the link is the master of the data
Control signals dir, stp, and nxt are specified with the assumption that the PhY is the master of the
interface, the control signal direction and protocol must be reversed
Signal
Direction
Description
PHY Interface
clock
O
Interface clock. Both directions are allowed. All interface signals are
synchronous to clock
Bi-directional data bus, driven low by the Link during idle. Bus ownership is
zero pattern onto the data bus. LPI defines interface timing for single-edge
determined by dir. The Link and PHY initiate data transfers by driving a nor
data transfers with respect to rising edge of clock. An implementation may
optionally define double-edge data transfers with respect to both rising and
falling edges of clock
Direction Controls the direction of the data bus when the phy has data to
transfer to the link, it drives dir high to take ownership of the bus. When the
dir
OUT
PhY has no data to transfer it drives dir low and monitors the bus for link
activity. The PhY pulls dir high whenever the interface cannot accept data
from the Link. For example, when the internal PHY PLL is not stable
Stop. The Link asserts this signal for 1 clock cycle to stop the data stream
currently on the bus. If the Link is sending data to the PHY, stp indicates the
stp
ast byte of data was on the bus in the previous cycle. If the Phy is sending
data to the link, stp forces the phy to end its transfer, de -assert dir and
relinquish control of thethe data bus to the Link
Next. The PhY asserts this signal to throttle the data When the link is
sending data to the PhY, nxt indicates when the current byte has been
nxt
OUT
accepted by the PHY. the Link places the next byte on the data bus in the
following clock cycle. When the PhY is sending data to the Link, nxt indicates
when a new byte is available for the link to consume
Table 1-LPl generic interface signals
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