MSP430_LaunchPad-ADC10 介绍.pdf此资料是本人在网上找到的，着重讲了MSP4

文件名称: MSP430_LaunchPad-ADC10 介绍.pdf

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详细说明：此资料是本人在网上找到的，着重讲了MSP430单片机ADC模块，对初学者非常有帮助TEXAS INSTRUMENTS ADC10 Registers www.ti.com 22.3 ADC10 Registers The ADC10 registers are listed in Table 22-3 Table 22-3. ADC10 Registers Register Short Form Register Type Address Initial State ADC 10 input enable register o ADC10AEO Read/w Reset with POr ADC10 input enable register 1 ADC10AE1 04Bh Reset with POR ADC10 control register o ADC1OCTLO Read/write 01B0h Reset with POr ADC10 control register 1 ADC1OCTL1 Read/write 01B2h Reset with POR ADC10 memory ADC1OMEM Read 01B4h Unchanged ADC10data transfer control register0ADClODTCO Read/write 048h Reset with POR ADC 10 data transfer control register 1 ADC1ODTC1 Read/write 049h Reset with POr ADC10 data transfer start address ADC10SA Read/write 01BCh 0200h with POR 558ADC10 SLAU144H-December 2004 Revised April 2011 Submit documentation Feedback Copyright a 2004-2011, Texas Instruments Incorporated TEXAS INSTRUMENTS www.ti.com ADC10 Registers 22.3.1 ADC10CTLO, ADC10 Control Register o 14 10 8 SREFX ADC10SHTX ADC10SRREFOUTREFBURST rw(0) rw. rw-(0) 5 MSC REF2 5V REFON ADC10ON ADC1OIE ADC1OIFG ENC A ADC10SC w-(0) rW-(0) rw-(0) Can be modified only when ENC =0 SREFX Bits 15-13 Select reference 000 VR+=Vcc and VR=V VREF+ and VR=v 010 VR+= VeREF+ and Ve =Vs and vo =ve VR+= Vcc and Ve-=vreF VeRE 110 VR.=VeREFt and Ve= VREF/ VerEf 111 VR+= Buffered VeREF, and VR=VRE/VeREF ADC10SHTx Bits 12-11 ADC10 sample-and-hold time 4×ADc10CLKs 8 x ADC10CLKs 16×ADc10CLk 64×ADc10CLKs ADC1OSR Bit 10 ADC10 sampling rate. This bit selects the reference buffer drive capability for the maximum sampling rate Setting ADC10SR reduces the current consumption of the reference buffer 0 Reference buffer supports up to -200 ksps Reference buffer supports up to -50 ksps REFOUT Bit 9 Reference output Reference output off Reference output on REFBURST Reference burst 0 Reference buffer on continuously Reference buffer on only during sample-and-conversiol MSC Bit 7 Multiple sample and conversion. valid only for sequence or repeated modes 0 The sampling requires a rising edge of the SHI signal to trigger each sample-and-conversion The first rising edge of the shi signal triggers the sampling timer but further ample-and-conversions are performed automatically as soon as the prior conversion is completed REF2 5V Reference-generator voltage. REFON must also be set 0 1.5V 2.5V REFON Bit 5 Reference generator on Reference off Reference ol ADC10ON ADC10 on ADC10 off ADC10 on ADC10IE Bit 3 ADC10 interrupt enable Interrupt disabled Interrupt enabled SLAU144H-December 2004 Revised April 2011 ADC10 Submit Documentation Feedback Copyright a 2004-2011, Texas Instruments Incorporated TEXAS INSTRUMENTS ADC10 Registers www.ti.com ADC1OIFG ADC10 interrupt flag. This bit is set if ADC10MEM is loaded with a conversion result. It is automatically reset hen the interrupt request is accepted, or it may be reset by software. When using the dtC this flag is set when a block of transfers is completed No interrupt pending Interrupt pending ENC Bit 1 Enable conversion ADC10 disabled ADC 10 enabled ADC 10S Bit o Start conversion Software-controlled sample-and-conversion start ADC10SC and ENc may be set together with one instruction. ADC10SC is reset automatically 0 No sample-and-conversion start start sample-and-conversion 560ADC10 SLAU144H-December 2004 Revised April 2011 Submit documentation Feedback Copyright a 2004-2011, Texas Instruments Incorporated TEXAS INSTRUMENTS www.ti.com ADC10 Registers 22.3.2 ADC10CTL1, ADC10 Control Register 1 14 10 8 INCHX ADC1ODF ISSH rw(0) rw. rw-(0) ADc10DⅣx ADC10SSELX CONSEQx ADC10BUSY w-(0) rW-(0) Can be modified only when ENC =0 Bits 15-12 Input channel select. These bits select the channel for a single- conversion or the highest channel for a sequence of conversions 0000A0 0001A1 0011A3 0101A5 0110A6 0111A7 1010 Temperature sensor 1011vc /2 1100(Vcc -Vss)/2, A12 on MSP430x22xX devices 1101 (Vcc-Vss)/2, A13 on MSP430x22xx devices 1110 (Vcc-Vss)/2, A14 on MSP430x22xx devices 1111(Vcc-Vss)/2, A15 on MSP430x22xx devices SHSX Bits 11-10 Sample-and-hold source select 00 ADC 10SC bit Timer A out1 10 Timer AOuto 11 Timer A OUT2 (Timer AOUT1 on MSP430x20X2 devices ADC1ODF ADC10 data format 0 Straight binary 2s complement ISSH Invert signal sample-and-hold The sample- input signal is not inverted input signal ADC10DIVX Bits 7-5 ADC10 clock divider 000 0114 1005 1016 7 1118 ADC1OSSELx Bits 4-3 adc0 clock source select ADC10OSC ACLK MCLK SMCLK SLAU144H-December 2004 Revised April 2011 ADC10561 Submit Documentation Feedback Copyright a 2004-2011, Texas Instruments Incorporated TEXAS INSTRUMENTS ADC10 Registers www.ti.com CONSEQx Bits 2-1 Conversion sequence mode select 00 Single-channel-single-conversion Sequence-of-channels Repeal-single-channel Repeal-sequence-or-channels ADC10BUSY Bit 0 ADC10 busy. This bit indicates an active sample or conversion operation A sequence, sample, or conversion is active 22. 3. 3 ADC10AEO, Analog(Input) Enable Control Register 0 7 6 5 4 3 1 0 ADC10AEOX rw-(0) (0) (0) rw-(0) ADC10AEOX Bits 7-0 ADC10 analog enable. These bits enable the corresponding pin for analog input. bITo corresponds to AO, BIT1 corresponds to A1, etc Analog input disabled Analog input enabled 22.3.4 ADC10AE1, Analog(Input) Enable Control Register 1(MSP430X22XX only ADC10AE1x Reserved rw-(0) r rw(0) (0) ADC10AE1x Bits 7-4 ADC10 analog enable. These bits enable the corresponding pin for analog input. blt 4 coresponds to a12, BIT5 corresponds to A13, BIT6 corresponds to A14, and BIT7 corresponds to A15 0 Analog input disabled Analog input enabled Reserved Bits 3-0 Reserved 22.3.5 ADC1OMEM, Conversion-Memory Register, Binary Format 15 10 Conversion Results rO 0 5 3 2 Conversion results Conversion Bits 15-0 The 10-bit conversion results are right justified, straight-binary format. Bit 9 is the MSB. Bits 15-10 are Results always 0 562ADC10 SLAU144H-December 2004 Revised April 2011 Submit documentation Feedback Copyright a 2004-2011, Texas Instruments Incorporated TEXAS INSTRUMENTS www.ti.com ADC10 Registers 22,3.6 ADC1OMEM, Conversion-Memory Register, 2s Complement Format 14 10 9 8 Conversion results 「50 r40 r00 Conversion Results 0 r rO rO Conversion Bits 15-0 The 10-bit conversion results are left-justified, 2s complement format. Bit 15 is the MSB Bits 5-0 are always Results 22.3. 7 ADC10DTCO, Data Transfer Control Register O 6 5 0 Reserved ADC10TB ADC10CT ADC10B1ADC10FETCH (0) Reserved Bits 7-4 Reserved. Always read as 0 ADC10TB ADC 10 two-block mode 0 One-block transfer mode Two-block transfer mode ADC10CT Bit 2 ADC10 continuous transfer Data transfer stops when one block (one-block mode)or two blocks(two-block mode )have Data is transferred continuously. DTC operation is stopped only if ADC10CT cleared, or ADC10SA is written to ADC10B1 Bit 1 ADC 10 block one. This bit indicates for two-block mode which block is filled with adc 10 conversion results ADC10B1 is valid only after ADC10lFG has been set the first time during DTC operation. ADC10TB must also be set Block 2 is filled Block 1 is filled ADC10FETCH Bit o This bit should normally be reset 22.3.8 ADC10DTC1, Data Transfer Control Register 1 7 6 5 4 3 0 DTC Transfers rW-(0) (0) rw(0) rw-(0) DTC Transfers Bits 7-0 Dtc transfers these bits define the number of transfers in each block DTC is disabled 01h-0FFh Number of transfers per block SLAU144H-December 2004 Revised April 2011 ADc10563 Submit Documentation Feedback Copyright a 2004-2011, Texas Instruments Incorporated TEXAS INSTRUMENTS ADC10 Registers www.ti.com 223.9 ADC10SA start Address Register for data Transfer 14 10 9 8 ADC 10SAX rW-(0) rw-(0) rw. rw-(0) ADC1OSAx 0 ADC1OSAX Bits 15-1 ADC10 start address. These bits are the start address for the DTC. a write to register ADC 10SA is required to initiate dTC transfers Unused Unused, Read only. Always read as O 564ADC10 SLAU144H-December 2004 Revised April 2011 Submit documentation Feedback Copyright a 2004-2011, Texas Instruments Incorporated

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