MC68020芯片手册MC68020芯片是80年代末90年代初摩托罗拉公司生产的一款32位微处理器，

文件名称: MC68020芯片手册

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详细说明：MC68020芯片是80年代末90年代初摩托罗拉公司生产的一款32位微处理器，大量用在了工业计算机上。现在市场上仍然有大量的设备控制部分使用的是MC68020芯片做主控CPU。本文档便是这款芯片的DATASHEET，用来做技术资料最为合适。9/29/95 SECtION 1: OVERVIEW UM Rey 1 TABLE OF CONTENTS Paragraph Page Number Title Number Section 1 Introduction Features.…1-2 1.2 Programming Model .B.8.8.8. Data Types and Addressing Modes Overview 18 Instruction Set Overview aa日 nn0000日a日aaaa:aa: nnn:aa: nnn I:a 1-10 Virtual Memory and virtual Machine Concepts 1-10 1.5.1 Virtual Memory ..:::日 .1-10 1.5.2 Virtual machine 1量面重111 1-12 1.6 Pipelined Architecture .1-12 1.7 Cache memo ry 1-13 Section 2 Processing States 2.1 Privilege Levels..… 2.1.1 Supervisor privilege Level ..2-2 2.1.2 User Privilege Level 2.13 Changing Privilege Level 2.2 Address space Types 23 Exception Processing 2-5 2.3.1 EXception Vectors 2-5 2.3.2 Exception Stack Frame .2-6 Section 3 Signal description 3.1 Signal Index… 3-2 3.2 Function Code Signals(FC2-FCo) 日· 3-2 3.3 Address Bus(A31-A0, MC68020)(A23-AO, MC68EC020) 3-2 3.4 Data bus(D31-D0)… 3-2 3.5 Transfer Size Signals(SIz1, sIzo 3-2 3.6 Asynchronous Bus Control Signals 画 R00 0_ 10000 0画画 10000 D画 annIn 3.7 Interrupt Control Signals…….……………………,……… 3.8 Bus Arbitration Control Signals 3-6 39 Bus Exception Control Signals 3-6 3.10 Emulator Support signal 3-7 3.11 Clock(CLK) MOTOROLA M68020 USER'S MANUAL 9/29/95 SECTION 1: OVERVIEW UM Rev. 1.0 TABLE OF CONTENTS (Continued) Paragraph Page Number Title Number 3.12 Power Supply Connections 3-7 3.13 Signal Summary 3-8 Section 4 On-Chip Cache Memory 4.1 On- Chip Cache Organization and operation……….…....… 4-1 4.2 Cache reset 4-3 4.3 Cache Control..…4-3 4.3.1 Cache Control Register(CACR) BE.888. 4-3 4.3.2 Cache Address Register(CAAR) 4-4 Section 5 Bus Operation 5.1 Bus Transfer Signals 5-1 5.1.1 Bus Control signals 5.1.2 Address bus a:aa:.aaaa:.a:aaaaaaa日a 5-3 5.13 Address strobe 5.1.4 Data bus 5-3 5.1.5 Data strobe ∴5-4 5.1.6 Data buffer enable 重1mmm 5-4 5.1.7 Bus Cycle Termination Signals 52 Data transfer mechanism 5.2.1 Dynamic Bus Sizing BBEI.I..B8I. 5-5 5.22 Misaligned Operands 4 52.3 Effects of Dynamic Bus Sizing and operand misalignment 5-20 5.2.4 Address, Size, and data Bus relationships 5-21 5.2.5 Cache Interactions 5-22 5.2.6 Bus Operation 5-24 5.2.7 Synchronous Operation with DSACK1/DSACKO ∴5-24 5.3 Data Transfer Cycles 5-25 5.3.1 Read cycle… 5-26 5.3.2 Write Cycle 5-33 5.3.3 Read-Modify-Write Cycle .5-39 5.4 CPU Space Cycles 5-44 5.4.1 Interrupt Acknowledge Bus Cycles. .......................................5-45 5.4.1.1 Interrupt Acknowledge Cycle--Terminated Normally 5-45 5.4.1.2 Autovector Interrupt Acknowledge Cycle 5-48 5.4.1.3 Spurious Interrupt Cycle..…….5-48 54.2 Breakpoint Acknowledge Cycle…….…..….….…...…..15-50 54.3 Coprocessor Communication Cycles 5-53 5.5 Bus exception Control cycles 5-53 5.5.1 BusErrorswwwwwwwwwwww.5-55 M68020 USERS MANUAL MOTOROLA 9/29/95 SECtION 1: OVERVIEW UM Rey 1 TABLE OF CONTENTS(Continued Paragraph Page Number Title Number 5.5.2 Retry operation .5-56 55.3 Halt Operation 5-60 5.54 Double bus fault. 5.6 Bus Synchronization 5-62 57 Bus arbitration 5-62 5.7.1 MC68020 Bus Arbitration 5-63 5.7.1.1 Bus Request MC68020 5-66 5.7.1.2 Bus grant(MC68020).…… 5-66 5.7.13 Bus grant Acknowledge(MC68020)……..…………5-66 5.7.1.4 Bus arbitration Control (MC68020 5-67 5.7.2 MC68EC020 Bus Arbitration.wm5-70 5.7.2.1 Bus Request(MC68EC020 ·== 5-71 5.7.2.2 Bus Grant(MC68EC020) 5-71 5.72.3 Bus arbitration contro(MC68Ec020)……5-73 5.8 Reset Operation 5-76 Section 6 EXception Processing 6.1 Exception Processing Sequence 6-1 6.1.1 Reset Exception 面重 6-4 6.12 Bus Error Exception....….……………6-4 6.1.3 Address Error Exception 1D重 6-6 6.14 Instruction Trap Exception .................................6-6 6.1.5 Illegal Instruction and Unimplemented Instruction Exceptions... 6-7 6.1.6 Privilege violation EXception…….….…..…...…...…6-8 6.1.7 Trace Exception .6-9 6.1.8 Format Error Exception .......................................................6-10 6.1.9 Interrupt EXceptions…….….….….………………………6-11 6.1.10 Breakpoint Instruction EXception 6-17 6.1.11 Multiple exceptions......................................6-17 6.1.12 Return from Exception -19 6.2 Bus Fault Recovery 6-21 6.2.1 Special Status Word(SSW)……… 6-21 6.2.2 Using Software to Complete the Bus cycles 6-23 62.3 Completing the Bus Cycles with RTE .6-24 6.3 Coprocessor Considerations. ..........................................................6-25 64 EXception Stack Frame Formats 6-25 MOTOROLA M68020 USER'S MANUAL X 9/29/95 SECTION 1: OVERVIEW UM Rev. 1.0 TABLE OF CONTENTS (Continued) Paragraph Page Number Title Number Section 7 Coprocessor Interface Description 7.1 Introduction 7.1.1 Interface Features .......,...................................................7-2 7.12 Concurrent Operation Support∴….…….…..….….….......7-2 7.1.3 Coprocessor System Interface∴…………………………………入 Coprocessor Instruction Format 7.1.4 7.1.4.1 Coprocessor Classification……..…...….....….....7-4 7.14.2 rocessor-Coprocessor Interface 7.1.4.3 Coprocessor Interface Register Selection................7-6 7.2 Coprocessor Instruction Types…………….…..…....….....7-7 7.2.1 Coprocessor General Instructions 7.2.1.1 Format 7-8 7.2.1.2 Protocol 7-9 7.2.2 Coprocessor Conditional Instructions 7-10 7.2.2.1 Branch on Coprocessor Condition Instruction 7-12 7.2.2.1.1 Format 7-12 7.2.2.1.2 Protocol 重■ 7-12 7.2.2.2 Set on Coprocessor Condition Instruction .........................7-13 7.2.2.2.1 Format3wwwww.ww7-13 7.2.2.2.2 Protocol 7-14 7.2.2.3 Test Coprocessor Condition, Decrement, and Branch Instruction.7-14 7.2.2.3.1 Format4..w.wwww.ww.7-14 7.2.2.3.2 Protocol..ww..w..mw..7-15 7.2.24 Trap on Coprocessor Condition Instruction ..............7-15 7.2.24 Format….7-15 7.2.2.4.2 Protocol..NNwNNwwwww7-16 7.23 Coprocessor Context Save and Restore Instructions 7-16 7.2.3.1 Coprocessor Internal State Frames 7-17 7.2.3.2 Coprocessor Format Words .7-18 723.2.1 Empty /Reset Format Word .7-18 7.2.3.2.2 Not-Ready Format Word 7-19 7.2.3.2.3 Invalid format word 7-19 7.2.3.2.4 Valid format word 7-20 7.2.3.3 Coprocessor Context Save Instruction................7-20 7.2.3.3.1 Format ……7-20 7.2.3.3.2 Protocol aaaaaa:aa:.aaaaaaaa:a“:a:aaaaaaaaa.a.:aaaa:aaa:aa 7-21 7.23.4 Coprocessor Context Restore Instruction 7-22 7.2.3.4.1 Format ….7-22 7.2.34.2 Protocol 7-23 7.3 Coprocessor Interface Register Set 7-24 M68020 USERS MANUAL MOTOROLA 9/29/95 SECtION 1: OVERVIEW UM Rey 1 TABLE OF CONTENTS (Continued Paragraph Page Number Title Number 7.3.1 Response CIR…… .7-24 7.3.2 Control cir 7-24 7.3.3 Save CIR 7-25 7.3.4 Restore CIR 7-25 7.3.5 Operation Word CIr 7-25 7.3.6 Command cir 7-25 7.3.7 Condition cir 7-26 7.38 Operand cir......... 7-26 7.3.9 Register Select CIR 7-27 7.3.10 Instruction Address cir 7-27 7.3.11 Operand Address CIR 7-27 74 Coprocessor Response Primitives. .............................................7-27 7.4.1 ScanPC a_.aa: nD日:aa:a: 100:aa: nnd: nnnn:a日:aa: nD.aaa日:aaa:a:.a:日aaa日aa 7-28 74.2 Coprocessor Response Primitive General Format 7-28 743 Busy Primitive… .. 7-30 74.4 Null Primitive∴.7-31 74.5 Supervisor Check Primitive…….…..…..…......17-33 746 Transfer Operation Word primitive .a=“ .7-33 7.4.7 Transfer from Instruction Stream Primitive 7-34 74.8 Evaluate and transfer effective Address primitive Evaluate Effective Address and Transfer Data Primitive 7-35 74.9 7-35 7.4.10 Write to Previously Evaluated Effective Address Primitive......7-37 7.4.11 Take address and transfer data primitive .7-39 74.12 Transfer to/from Top of Stack Primitive 1重日重菌B首面 7-40 74.13 Transfer Single Main Processor Register Primitive 7-40 7.4.14 Transfer Main Processor Control Register Primitive. ....................7-41 74.15 Transfer Multiple Main Processor Registers Primitive 7-42 74.16 Transfer Multiple Coprocessor Registers Primitive 7-42 7.4.17 Transfer Status Register and ScanPC Primitive...........7-44 7.4.18 Take Preinstruction EXception Primitive……,…,…,…,…,,.,.1-45 74.19 Take Midinstruction EXception Primitive...........-.7-47 7.4.20 Take Postinstruction Exception Primitive .....................................7-48 7.5 Exceptions .7-49 7.5.1 Coprocessor-Detected Exceptions 7-49 7.5.1.1 Coprocessor-Detected Protocol Violations .7-50 7.5.1.2 Coprocessor-Detected lllegal Command or Condition Words...7-51 7.5.1.3 Coprocessor Data-Processing-Related EXceptions .:: 7-51 7.5.14 Coprocessor System-Related Exceptions .7-51 7.5.1.5 Format errors ∴7-52 7.52 Main- Processor- Detected Exceptions………. 7-52 7.5.2.1 Protocol violations 7-52 7.5.2.2 F-Line Emulator Exceptions 7-54 MOTOROLA M68020 USER'S MANUAL 9/29/95 SECTION 1: OVERVIEW UM Rev. 1.0 TABLE OF CONTENTS (Continued) Paragraph Page Number Title Number 7.5.2.3 Privilege violations 7-55 75.2.4 cpTRAPcC Instruction Traps ..7-55 75.2.5 Trace EXceptions...….…....7-55 7.52.6 interrupts∴ 7-56 7.5.2.7 Format errors .重1重D,重 7-57 752.8 Address and Bus errors a:.:a日:aaa .7-57 7.53 Coprocessor Reset 17-58 7.6 Coprocessor Summary… 7-58 Section 8 Instruction Execution Timing 8.1 Timing Estimation Factors…….… 8-1 8.1.1 Instruction Cache and Prefetch 8-1 8.1.2 Operand misalignment 8-2 8.1.3 Bus/Sequencer Concurrency 重1日重重日1自1日1n日 8-2 8.1.4 Instruction EXecution Overlap 8.1.5 Instruction Stream Timing Examples 重面m .... 8-4 8.2 Instruction Timing Tables 8-9 8.2.1 Fetch effective Address wwwwwwwwwwwm8-13 8.2.2 Fetch Immediate Effective address 8-14 8.2.3 Calculate effective Address 8-16 8.2.4 Calculate Immediate effective address 8-17 82.5 Jump Effective Address 8-19 82.6 MOVE Instruction .. 8-20 8.2.7 Special-Purpose MOVE Instruction 8-29 8.28 Arithmetic/Logical Instructions .8-30 8.2.9 Immediate Arithmetic/Logical Instructions 8-31 8.2.10 Binary-Coded Decimal Operations :aa:aa:aaaaa::a:aa:aaaa:aaaaaaaaaa 8-32 8.2.11 Single-Operand Instructions .8-33 8.2.12 Shift/Rotate Instructions .8-34 8.2.13 Bit Manipulation Instructions...............................8-35 8.2.14 Bit Field Manipulation Instructions 8-36 8.2.15 Conditional branch Instructions 8-37 8.2.16 Control Instructions 8-38 8.2.17 EXception -Related Instructions 8-39 8.2.18 Save and Restore Operations 8-40 Section 9 Applications Information Floating-Point Units 9-1 92 Byte Select Logic for the MC68020/EC020 9-5 9.3 Power and ground considerations 9-g M68020 USERS MANUAL MOTOROLA 9/29/95 SECtION 1: OVERVIEW UM Rey 1 TABLE OF CONTENTS (Concluded) Paragraph Page Number Title Number 94 Clock Driver B重面 9-10 95 emory Interface 9.6 Access Time calculations 9-12 9.7 Module Support……… 9-14 9.7.1 Module Descriptor. 9-14 97.2 Modulestackframewwwwwww.9-16 98 Access levels…1 9-17 9.8.1 Module call 9-18 98.2 Module return 9-19 Section 10 Electrical Characteristics 10.1 Maximum Ratings 10-1 10.2 Therma| Consideratⅰons… ..10-1 10.2.1 MC68020 Thermal Characteristics and DC Electrical characteristics .10-2 10.2.2 MC68EC020 Thermal characteristics and DC Electrical Characteristics 10-4 10.3 AC Electrical Characteristics 10-5 Section 11 Ordering Information and Mechanical Data Standard Ordering Information 11-1 11.1.1 Standard MC68020 Ordering Information 1.1.2 Standard mC68EC020 Ordering Information 11.2 Pin Assignments and Package Dimensions…… 112 11.2.1 MC68020 RC and rP Suffix-Pin assignment .11-2 1.2.2 MC68020 RC Suffix-Package Dimensions 11-3 112.3 MC68020 RP Suffix-Package Dimensions aaaa“aaaa 11-4 11.24 MC68020 FC and FE Suffix--Pin assignment 11-5 11.2.5 MC68020 FC Suffix- Package Dimensions……116 11.2.6 MC68020 FE Suffix--Package Dimensions 11-7 11.2.7 MC68EC020 RP Suffix-Pin Assignment .11-8 1.2.8 MC68EC020 RP Suffix-Package Dimensions .......................11-9 11.2.9 MC68EC020 FG Suffix--Pin Assignment .1110 11.2.10 MC68Ec020 FG Suffix- Package Dimensions………....111 Appendix A Interfacing an MC68EC020 to a DMA Device That Supports a Three-Wire Bus Arbitration Protocol MOTOROLA M68020 USER'S MANUAL 9/29/95 SECTION 1: OVERVIEW UM Rev. 1.0 LIST OF ILLUSTRATIONS Fiqure Page Number Title Number 1-1 MC68020/EC020 Block Diagram 1-2 User Programming Model…… 1-3 Supervisor Programming Model Supplement 4 Status Register(SR)……… a:1 ..B:aa:aa:aa“日.日:日1..... 1-5 Instruction Pipe 113 2-1 General Exception Stack Frame 2-6 3-1 Functional Signal groups 3-1 1 MC68020/EC020 On-Chip Cache Organization 4-2 4-2 Cache Control Register 重■重 4-3 4-3 Cache Address Register..….…… 4-4 5-1 Relationship between External and Internal signals 5-2 Input Sample Window…… 5-2 5-3 Internal Operand Representation MC68020/EC020 Interface to various port sizes 5-6 5-5 Long-Word Operand Write to Word port example 重D日D1m重 I.B.88888 10 5-6Long- Word operand Write to Word port Timing……………….5-11 5-7 Word Operand Write to Byte Port Example 5-12 5-8 Word operand Write to Byte port timing..................5-13 5-9 Misaligned Long- Word operand Write to Word port EXample……………….5-14 5-10 Misaligned Long-Word Operand Write to Word port Timing 5-15 5-11 Misaligned Long-Word operand read from Word port example 5-16 12 Misaligned Word operand Write to Word port Example 5-16 5-13 Misaligned Word operand write to Word port timing 5-17 5-14 Misaligned Word operand read from Word Bus Example.........5-18 5-15 Misaligned Long-Word operand Write to Long-Word port Example 5-18 5-16 Misaligned Long-Word operand Write to Long-Word port Timing ................5-19 5-17 Misaligned Long-Word Operand read from Long-Word port Example....5-20 5-18 Byte Enable Signal Generation for 16-and 32-Bit Ports 5-23 5-19Long- Word Read Cycle Flowchart……………………………5-26 5-20 Byte Read cycle Flowchart 5-27 5-21 Byte and Word read cycles--32-Bit Port BBI.....I 5-28 5-22 Long- Word Read--8-Bit Port 5-29 5-23 Long-Word Read-16-and 32-Bit Ports 5-30 M68020 USERS MANUAL MOTOROLA

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