W5500-en.pdfw5500数据手册WIZnet Target Applications W5

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详细说明：w5500数据手册WIZnet Target Applications W5500 is suitable for the following embedded applications Home Network Devices: Set-Top Boxes, PVRs, Digital Media Adapters Serial-to-Ethernet: Access Controls, LED displays, Wireless AP relays, etc Parallel-to-Ethernet: POS /Mini Printers, Copiers USB-to-Ethernet: Storage Devices, Network Printers GPIO-to-Ethernet Home network sensors Security Systems: DVRs, Network Cameras, Kiosks Factory and Building automations Medical Monitoring Equipment Embedded servers W5500 Datasheet Version 1.0.7(FEB 2016 3/66 WIZnet Block Diagram Host SPI Interface SPI Interface manager 150MH Register Manager 25MHZ PLL TCP/IP Core UDP TCP ICMPIGMP V1/V2 PPPoE ARP 3.3￥ Power 802.3 Ethernet MAC Regulator 1.2￥北 MIl Manager (CSMA/CD) Ethernet PHY Media Interface Transformer RJ45 4/66 W5500 Datasheet Version1.0.7(FEB 2016) WIZnet Table of contents 1 Pin Assignment...................,.... Pin Descriptions∴…,…,,,,,…,…,…,,,,,7 2 HOST Interface……,…,…,…,……,……………,2 2.1 SPl Operation Mode.. n13 SPI Frame 4 2.2. Address phase 4 2.2.2 Control phase . 2.2.3 Data phase 2.3 Variable Length Data Mode(VDM).……………………17 2.3.1 Write access in VdM 18 2.3.2 Read access in vdm Fixed Length Data Mode(FDm) 24 2.4.1 Write access in fdm 25 2.4.2 Read Access in FDM 26 3 Register and memory Organization,,,…,,,,…,…,,,…,,………27 3.1 Common register Block 29 3.2 Socket Register Block ··..···.···············.··········.···.··.···4·· 3.3 Memory……………… 4 Register Descriptions 4.1 Common Registers∴, 32 4.2 Socket Registers .......................,.... 看。看申。垂看· 5 Electrical Specifications∴,,…,,…,…,…………58 Absolute maximum Ratings . .............................................................58 5.2 Absolute Maximum Ratings( Electrical sensitiⅳity)……….58 5.3 DC Characteristics ··垂非··看垂 5.4 Power dissipation................. 60 5.5 AC Characteristics 5.5.1 Reset Timing……......………60 5.5.2 Wake up Time..... 5.5. 3 Crystal Characteristics....,...........,........ 非d非 5.5.4 SPI Timing 61 5.5.5 Transformer characteristics .62 5.5.6MDX 6 IR Reflow Temperature Profile(Lead-Free).....,........ ●看·D·看·D·看 63 7 Package Descriptions 64 Document History Information∴……………………………………65 W5500 Datasheet Version 1.0.7(FEB 2016 5/66 WIZnet Table of Figures Figure1.W5500 Pin Layout….…………, Figure 2. External reference resistor..... Figure 3. Crystal reference schematic Figure 4. Variable Length Data Mode(sCSn controlled by the host)....... 12 Figure 5. Fixed Length Data Mode(SCSn is always connected by ground)..... 12 Figure 6. SPI Mode 0 it 3 13 Figure 7. SPl Frame Format 14 Figure 8. Write SPI Frame in VDm mode ∴18 Figure 9. SIMR Register Write in VDM Mode..,......................19 Figure 10. 5 Byte Data Write at 1th Sockets TX Buffer block 0X0040 in VDM mode. 20 Figure 11. Read SPl Frame in VDM mode... · 21 Figure 12. S7_SR Read in VDM Mode 22 Figure 13. 5 Byte Data Read at Socket 3 RX Buffer block 0x0100 in VDM mode ..,. 23 Figure 14.1 Byte Data Write SPI Frame in FDM mode. 25 Figure15.2 Bytes Data Write SPI Frame in FDM mode..….….…....…..25 Figure 16. 4 Bytes data Write spi frame in FDm mode...................25 Figure 17. 1 Byte Data Read SPl Frame in FDM mode 26 Figure 18. 2 Bytes Data Read SPI Frame in FDM mode...,.............. 26 Figure 19. 4 Bytes Data Read sPI Frame in FDM mode..... ∴26 Figure 20 Register a Memory organization .................................................28 Figure 21. INTLEVEL Timing 34 Figure22. Reset Timing.…,…,,,,, Figure23. SPI Timing.…,,,…61 Figure 24. Transformer Type 62 Figure25. IR Reflow Temperature………… Figure 26. Package Dimensions.,……,64 6/66 W5500 Datasheet Version1.0.7(FEB 2016) WIZnet Pin Assignment 1 36 TXP 35 MOSI AGND AVDD SCLK RXN 32 SCSn RXP W5500 31 XO DNC XI/CLKIN AVDD 48LOFP 29 GND AGND VDD 27 ACTLED AVD匚11 DUPLED 25 LINKLED Figure 1. w5500 Pin Layou 1.1 Pin Descriptions Table 1. Pin type notation Type Description Input Output vO Input / Output A Analog PWR 3. 3V power GND W5500 Datasheet Version 1.0.7(FEB 2016 7/66 WIZnet Table 2. W5500 Pin Description Internal Pin no Typ Description Bias TXN Ao TXP/TXN Signal Pair TXP Ao The differential data is transmitted to the media on the TXP/TXN signal pair. AGND GND Analog ground 4 AyDD PWR Analog 3. 3V power RXN Al RXP/RXN Signal Pair RXP Al The differential data from the media is received on the RXP/RXN signal pair. 7 DNC Al/o Do Not Connect Pin 8 AdD PWR Analog 3. 3V power AGND GND Analog ground 10 EXRES1 Al/O External Reference Resistor It should be connected to an external resistor( 12. 4KQ2 1%)needed for biasing of internal analog circuits. Refer to the 'External reference resistor(Figure 2)for detaills 11 AVDD PWR Analog 3. 3V power Nc 13 NC 14 AGND GND Analog ground 15 AdD PWR Analog 3. 3v power 16 AGND GND Analog ground 17 AVDD PWR Analog 3. 3V power 18 VBG AO Band Gap Output Voltage This pin will be measured as 1.2V at 25C It must be left floating 19 AGND GND Analog ground 20 TOCAP AO External Reference Capacitor This pin must be connected to a 4.7uF capacitor. The trace length to capacitor should be short to stabilize the internal signals 21 AVI DD PWR Analog 3. 3V power 1Y20 AO 1.2V Regulator output voltage Internal Bias after hardware reset 8/66 W5500 Datasheet Version1.0.7(FEB 2016) WIZnet This pin must be connected to a 1onF capacitor This is the output voltage of the internal regulator. 23 RSVD Pull-down I It must be tied to GND. 24 SPDLED o Speed LED This shows the Speed status of the connected link Low: 100Mbps High: 10Mbps 25 LINKLED o Link LED This shows the link status Low: Link is established High: Link is not established 26 DUPLED o Duplex LED This shows the duplex status for the connected link Low: Full-duplex mode High: Half-duplex mode ACTLED 0 Active LED This shows that there is Carrier sense (CRS) from the active Physical Medium Sub-layer(PMD)during tX or RX activit Low: Carrier sense from the active pmd High: No carrier sense 28 VDD PWR Digital 3.3V Power 29 GND GNDDigital Ground 30XI/CLKIN Al Crystal input /External Clock input External 25MHz Crystal Input. This pin can also be connected to single-ended ttl oscillator( CLKIN) 3. 3v clock should be applied for the EXternal Clock input. If this method is implemented, XO should be left unconnected Refer to the 'Crystal reference schematic'(Figure 3)for details 31 Ao Crystal output External 25MHz Crystal Output Note: Float this pin if using an external clock being driven through XI/CLKIN 32 SCSn Pull-up Chip select for SPl bus This pin can be asserted low to select w5500 in SPl interface Low: selected W5500 Datasheet Version 1.0.7(FEB 2016 9/66 WIZnet High: deselected 33 SCLK SPl clock input This pin is used to receive SPI Clock from SPl master 34 MISO o SPI master input slave (w5500 )output When SCSn is Low, this pin outputs SPI data When SCSn is High, this pin becomes High Impedance (logically disconnected) 35 MOSI I SPl master output slave(w5500) input 36 INTn 0 Interrupt output (Active low Low: Interrupt asserted from w5500 High: No interrupt 37 RSTn Pull-up Reset (Active low) RESeT should be held low at least 500 us for W5500 reset 38 RSVD Pull-down NC 39 RSyD Pull-down I Nc RSVD Pull-down I NO RSVD Pull-down NC 42 RSVD Pull-down I NC 43 PMODE2 Pull-up I PHY Operation mode select pins 44 PMODE1 Pull-up I These pins determine the network mode. Refer to the PMODEo Pull-up below table for details PMODE [2: 0 Description 210 0 00 10BT Half-duplex, Auto-negotiation disabled 0 1 10BT Full-duplex, Auto-negotiation disabled 01 0 100BT Half-duplex, Auto-negotiation disabled 0 11 100BT Full-duplex, Auto-negotiation disabled 1 00 100BT Half-duplex, Auto-negotiation enabled 0 1 Not used 10 Not used All capable, Auto-negotiation enabled 46 NC 47 NC 48 AGND GND Analog ground 10/66 W5500 Datasheet Version1.0.7(FEB 2016)

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