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文件名称: AN_377 Altera FPGA FIFO master Programming Guide.pdf
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  上传时间: 2019-08-24
  提 供 者: gaojie*******
 详细说明：FT601Q Altera FPGA FIFO master Programming GuideFTDI AN 377 Altera FPGA FIFo master Programming guide Chip Version 1.0 Document Reference No. ft 001194 Clearance No. FTDI#463 1 Introduction This document explains how to use the altera Quartus II Programmer to program an Altera FPGa as a FIFo master with a sample image compatible with interfacing to either a UMFT600A or UMFT601A module 11 Overview The UMFT600A/UMFT601A modules are evaluation modules with HSMc high speed connectors, providing UsB30 to 16Bit/32Bit wide parallel FIfo interfaces, which are used to evaluate the functiona lity of FT600/ FT601 device As a FIFo slave board, the UMFT600AUMFT601A operates with a FIFo master board which has a standard HSMc connector. This document explains how to program an Altera FPGa Board(cyclone v Gx Starter Kit as a FIFo master with the sample image so that the user can run the FT600DataLoopbackApp to verify modules functions 1.2 Prerequisite A PC with Altera Quartus II Programmer(Assume Altera drivers have been installed. Altera Cyclone v gX starter Kit 1.3 Notes FTDI provides 4 different FPGA loopback application images and 2 PCB evaluation boards with an HSMc connector that is compatible with Altera FPGa development kits. Ensure the FPGA image used matches with the pcb evaluation board l.e. umft6oo or umft6o1 and either 600 mode or 245 mode of operation data transfer will not work properly if the fpga image is incompatible with the pcb evaluation board FPGA loopback application images Altera FPGA-Cyclone v starter kit C5G, FT601, 600 mode Altera FPga-Cyclone v starter kit C5G, F601, 245 mode Altera FPGA-Cyclone v starter kit C5G, FT600, 600 mode Altera FPGA-Cyclone v starter kit C5G, FT600, 245 mode PCB evaluation boards UMF T601A(HW 432)-For Altera FPGa with Ft601 image UMFT60OA(HW_430)-For Altera FPGA with FT600 image Copyright 20 15 Future Technology Devices International Limited FTDI AN 377 Altera FPGA FIFo master Programming guide Chip Version 1.0 Document Reference No. ft 001194 Clearance No. FTDI#463 2 Step-by-step instruction 1. Connect the Cyclone v GX Starter board ]10(USB blasteR to a PC with a USB cable 2. Push SW11 to the prog position for flash programming and the run position for FPGa programming and loopback test 3. Plug in a 12V dC supply to J9, then turn on the poWer(press sw10) 4. All other sw and Jumpers on board should be default factory settings USB TO PC RUN-PROG DC12 IN POWER SW cron 8: m“智 a剧 想想 AURA ma SSI Cyclone. CGXECSC6E27C1N m NUTBRA 当算与,含 Figure 2.1 Cyclone V GX Starter board Hardware Setup Copyright 20 15 Future Technology Devices International Limited FTDI AN 377 Altera FPGA FIFo master Programming guide Chip Version 1.0 Document Reference No. ft 001194 Clearance No. FTDI#463 5. Run the Qu II Programmer, the hard (USB-Blaster [USB-11) should be found automatically, and then select Mode Active Serial Programming for programming flash G for programming FPG "iP +: view Pro"song cnls Window HAp 立H:5Ls日erE4 F Anhe real-time l P m all w hark cind programming whe Checksum fy Blank- o Start Che=k 学 Auto Detect I Message a\ sys tem /T P-ocessra Quartu: I 64-0it Programtr-IChainlcdf ,,, Ele Edi: View Processing Tools Window H=b 9 Seara alt 盒 Hardware Setup.。U8eusB们 Mode: JTAG L Enabla real-time ISF to all w backgro nd programming when avaiable DEvice ogram/ Vcrf Bank omm start Check C Stop Auto Detect 减=lpte n Add filc Crange file Save Fle C Adc Device.. M只只A了色 SYEtem/、 Processing Figure 2.2 Select Program Mode Copyright 20 15 Future Technology Devices International Limited FTDI AN 377 Altera FPGA FIFo master Programming guide Chip Version 1.0 Document Reference No. ft 001194 Clearance No. FTDI#463 6. Click the Add file. icon to specify the file for flash(. pof)or FPGAC. sof), and the device will be added automatically. 7. Click 'Start to program the selected device Quartus I 64-Lit Programmer-IChainI cdf] Hle dirt vew Pressing orks window Help Searchalrcra.com Modc: Active Se ial Program F Enable real-tima ISP to allow backg ound programming when available Cre-ksum cgam/ ou Start Ay Delect x Dells Acd device ASD sQ255 x如回圆圆画 to allow Eackcrourd programmng when available Verify bla 怕5 Delete LYsaveFle owr sRn/、 Processing7 Figure 2.4 FPGA Programming Copyright 20 15 Future Technology Devices International Limited FTDI AN 377 Altera FPGA FIFo master Programming guide Chip Version 1.0 Document Reference No. ft 001194 Clearance No. FTDI#463 8. Program successfully A-Bi 5. oufarnr =lc Ecit Vicw Proccaarg Toab Window: Heb sparc atera co Mode:artu=Pal -ngamring progress:103%.surress'u) M Enable eal-time ISP to alcu background procrammro when avallable yu Start FaMiNe Checo GilFToo3_ master cydon.[PCC25G ors LD2D52000c00 →日 TP工D 1Kn图 HrnnraTmer narat: nn at TA Ap141:14:用15 Fit EL Ven PrJuessir Twvls Wir un HelL Search alteram Setup.USB-Blaster[LS3-C regess 100%uccessful) F Enable rea- ime ISP o allow ba=kcrounc programming/ tor MAXI: and MAX V devices ChecO C: T600_master_cydcn. 5CGXFC5CEF27 00D212A7 002212A7 Ay Aut Detect Delete C Add Device I ↓Dn (D 209061 Ended Programer operacion at Iue Ipr 14 15: 24: 14 2015 System(13八? recessing Figure 2.5 Program Successfully Copyright 20 15 Future Technology Devices International Limited FTDI AN 377 Altera FPGA FIFo master Programming guide Chip Version 1.0 Document Reference No. ft 001194 Clearance No. FTDI#463 3 UMFT6OOAUMFT6O1A Data Loopback Demo 1. Hardware setup: Connect the UMFT600A or UMFT601A module to the altera Cyclone V GX Starter board: connect the UMft601a or uMft601A cn1 to the pc with a micro-USB30 cable. Plug in a 12V DC supply to ]9 on the Altera Cyclone V Gx Starter Board, and then turn on the power 8 FTDI 要2AbRA Figure 3.1 UMFT600A/UMFT601A data loopback demo hardware setup 2. Run 'FT600DataLoopbackApp' the application will find the device automatically click the Start All'button to do all channels data loopback test Please refer to AN 375 FT600 Data Loopback Application User Guide for more details of this application ●FT600 Data Loopback ID0s0402 Data Transfer □ Random Lengt MEGc" FO SEc erice not connected y uaing D:vicc atDI FEN LY GLID:亿2Ec-EC9D工727LZCE0升 厂 Show webg tonso dea>uψyuL Figure 3.2 FT600 Data loopback application Copyright 20 15 Future Technology Devices International Limited FTDI AN 377 Altera FPGA FIFo master Programming guide Chip Version 1.0 Document Reference No. ft 001194 Clearance No. FTDI#463 4 Contact information Head office- Glasgow, UK Branch Office Tigard, Oregon, USA Future Technology Devices International Limited Future Technology Devices International Limited Unit 1 2 Seaward place centurion business park (USA Glasgow g41 1HH 7130 SW Fir Loop United Kingdom agard,OR97223-8160 Te:+44(0)1414292777 USA Fax:+44(0)1414292758 Te:+1(503)5470988 Fax:+1(503)5470987 E-mail(sales) sales1(ftdichip.com E-mail (Support support1ftdichip.com E-Mail (sales) us.salesftdichip.com E-mail(generalEnquiriesadmin1ftdichip.com E-Mail(Support) ussupportftdchip.com E-Mail(General Enquiries Us.adminftdichip.com Branch Office- Taipei, Taiwan Branch Office- shanghai, china Future Technology Devices International Limited Future Technology Devices International Limited China) 2F No, 516, Sec. 1, NeiHu road Room 1103, No 666 West Huaihai road Taipei 114 Shanghai, 200052 Taiwan, R.O.c China Te:+886(0)287913570 Te|:+862162351596 Fax:+886(0)287913576 Fax:+862162351595 E-mail (Sales tw.sales1(ftdichip.com E-mail (sales) cn.salesftdichip.com E-mail(Support) twsupport1ftdichip com E-mail (support) cn.supportftdichip.com E-mail(General Enquiries) tw admin 1(ftdichip com E-mail(generalEnquiriescn.admin(ftdichip.com Web site http://ftdichip.com Distributor and sales Representatives Please visit the sales Network page of the ftDi Web site for the contact details of our distributor(s )and sales representative(s)in your country System and equipment manufacturers and designers are responsible to ensure that their systems, and any Future Technology Devices International Ltd (FTDI)devices incorporated in their systems, meet all applicable safety regulatory and system-level performance requirements. All application- related information in this document(including application descriptions, suggested FTDI devices and other materials) is provided for reference only. While FtDi has taken care to assure it is accurate, this information is subject to customer confirmation and FtDi disclaims all liability for system designs and for any applications assistance provided by FTDI. Use of FtDi devices in life support and or safety applications is entirely at the users risk, and the user agrees to defend, indemnify and hold harmless FTDI from any and all damages, claims, suits or expense resulting from such use. This document is subject to change without notice. No freedom to use patents or other intellectual property rights is implied by the publication of this document. Neither the whole nor any part of the information contained in, or the product described in this document, may be adapted or reproduced in any material or electronic form without the prior written consent of the copyright holder. Future Technology Devices International Ltd, Unit 1, 2 Seaward Place, Centurion Business Park, Glasgow G41 1HH, United Kingdom. Scotland Registered Company Number: SC136640 9 Copyright 20 15 Future Technology Devices International Limited FTDI AN 377 Altera FPGA FIFo master Programming guide Chip Version 1.0 Document Reference No. ft 001194 Clearance No. FTDI#463 Appendix a Document References AN 375 FT600 Data Loopback Application User Guide DS UMFT60xx module datasheet D3XX Programmer's Guide an 385 D3XX Installation guide ALTERA Firmware download Loopback utility C5G User Manual Acronyms and abbreviations Terms Description FIFO First in first out FPGA Field Programmable Gate Array HSMC High Speed Mezzanine Card JTAG Joint Test Action Group USB Universal serial bus 10 Copyright 20 15 Future Technology Devices International Limited
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