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详细说明：Data acquisition and high speed storage by FPGA implementation in the Quadrupole mass spectrometryApplied Mechanics and Materials vols. 239-240 903 In the reading control module, the read enable signal (reading signal address selection signal) is used to trigger out the reading trigger signal. When the address selection signal and reading signa both become low, the reading trigger signal will be sct to l at the rising edge of the first clock, and will be set o at the rising edge of the second clock. So the rising edge of the clock signal can be contained by the reading trigger signal. when the reading trigger signal is set to 1, the rising edge of the system clock will cause FIfO to put out a stored data. Reading trigger signal is ready ahead of 20ns than the rising edge of system clock, so it can read the data out from built-in FIfo memory In order to avoid the data conflict, the output data from FiFo is connected to mcs data bus acoss tri-state buffers. The control port of tri-state buffer is controlled by the read enable signal. When address selection signal and reading signal both become low, MCS will read the data out from FIFO In the writing control module, the writing enabling signal is used to trigger out the writing trigger signal. When the writing enabling signal becomes low, state machine will set the writing trigger signal to 1 on the rising edge of the second clock, and set it too on the rising edge of the third clock Writing trigger signal is generated ahead of 20ns before the rising edge of system clock. It satisfies timing requirement of writing data. When the writing trigger signal becomes high, the rising edge of the system clock will write the sampled ms parallel data into FIFO automatically Status flags generation module. The built-in FIFO memory can automatically generate Empty and Full status flags. The storage counter can generate Half Full and Overflow status flags. MCS judges the FIFO storage status depend on status flags. When the top bit of storage counter is high, it represents that the storage status exceed half full. But when FIFo overflows, the top bit of storage counter will be set to zero. So the top bit of storage counter need to be or with full status flag bit to generate half full status flag bit. The algorithm of status flags generation is showed in Eq. 1 Addwrite Addread= num When num=0. EF=LHF=0.FF=0 When 0< num r 4K. EF=0.HF=0.FF=0 When 4k< numao 8k,EF=0, HF=1,FF=O When num cc =8K. EF=OHF=LFF=1 The experimental results and data analvsis We had sclected EP1C20(Altera company, American) as main control platform. It has integrated the static ram of 36k bits The total FPga control module has realized the built-in Fifo memory of 8K16 bits, and has supported simultaneously maximum reading and writing speed of 60Mbps In the Qms instrument design, we had used two design methods. The first method is using FPga internal static RAM memory as FIFO Storage memory, and the second method is using external SRAM memory as FIFO memory[7]. The PFGA internal resources utilization and performance of two methods is compared and the result is listed in Table 1 Table 1. FPGa internal resources utilization and performance Built-in fifo buffer External sram as a Factor data method FIFO buffer method simultaneous read and write speed [ns] 15 storage capacity [bit 8K16 1024KXl6 Used FPGA logic unit 162 204 FPGA Storage unit [bit] 8K×16 0 Used pll in fpga 0 Time of buffering data [ms] 5000 (200ksps sampling rate As shown in table 1. the method which has used fPga internal static RaM units as the built-in FIFO memory, has lightweight structure of the programming, and has the advantage on high-speed of simultaneously reading and writing. But the Fifo memory only realizes a small storage capacity of 904 Measurement Technology and its application 8k16 bits. The control system which had controlled external SraM as FIfO memory, had realized 128 times FIFO capacity than the former design. Both of them cost almost one percent of fPGa logic units. For 200Ksps sampling rate, the Fifo memory of 8k 16 bits can only buffer the ms data of 40ms. The system which uses FPGA internal RAM units as built-in FIFO memory, has lightweight structure, and supports high-speed of simultaneously reading and writing. The capacity can basically satisfy the requirements of QMs Using data acquisition and storage control system, National Institute of Metrology(NIM) had developed the pec-LC-T MS of electrospray ionization(ESI)-rectilinear ion trap(rit)Ms. MrFa MS had been detected on pec-LC-T MS, as it is shown on Fig. 2 524.3 12.0- 10.0 610uV 0 5253 4.0 526.3 0. 510 515 m/z(Thomson) Fig. 2. MRFA MS obtained on a spec-LC-T Conclusion Compared with the method of using external SraM as a FiFO buffer, the method of built-in FIFO memory has lightweight structure, and it is more conducive to rapid development. Although data storage capacity of the built-in FIFO memory is much smaller, it supports maximum simultaneously reading and writing speed of 60Msps. The capacity can basically satisfy the storage capacity requirements of QMs. The control system of data acquisition has been applied to El-Rit, ESI-RIt and many other types of Qms developed by nim References [1] B.J. Wu. Doctor thesis. Jilin University, 2010 2 Y.H. Gao, B.J. Wu, YJiang. High performance data acquisition system in the quadrupole mass spectrometer(Changchun: Journal of jilin University(Engincering and technology edition)), 2009, pp 628-633 3]BJ. Wu, JIang, Y H Gao. Low-noise and wide-band design of composite preamplifier in the Quadrupolar mass spectrometer(Changchun: Optics and precision engincering), 2008,pp 1767-1772 14] P.J. Zhu. Doctor thesis. Southeast University, 2004 5]Brian H Clowers, W.F.S., Herbert H Hill and Steven M. Massick 2006 Hadamard Transform lon Mobility spectrometry Analytical chemistry, Vol. 78, No 1, pp 44-51 6 S.J. Ren, Y.J.Ren, W.J.Hu. USing CPLD and external sraM to desigh high-volume FIFO Design prespectives), 2001, pp 15-17. 7 YHGao, B.J. Wu, YJiang. High performance data acquisition system in the quadrupole mass spectrometer(Journal of Jilin University (Engineering and technology edition)), 2009, pp 206-209 Measurement Technology and its Application 10.4028/www.scientific.net/amm.239-240 Data Acquisition and High Speed Storage by FPGA Implementation in the Quadrupole Mass pectrometry 10.4028/www.scientificnet/amm.239-240.901

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