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详细说明：F1C600 User Manual，F1C600芯片使用手册，含寄存器等编程信息。Allwinner
Technology
Revision History
Revision history
Version
ate
Description
V1.0
NoV10,2015
nitia|Re|ease∨ersⅰon
F10600 User Manual( Revision 1.0)
Copyright O2015 Allwinner Technology. Co, Ltd. All Rights Reserved
Page 3
Allwinner
Technology
Revision History
Table of contents
Declaration
2
Revision histe
D。着,着垂
Table of contents
.:::::.:::::1:
4
Chapter 1.About This Documentation
36
1.1 Documentation overview
36
Chapter 2 Overview...
.37
2.1 Processor features
2.1.1, CPU Architecture
2.2. Memory Subsystem....................
38
2.2.1. Boot rom
38
2.2.2 SDRAM
38
2.2.3. SD/MMC Interface
..:::··:·.:::::..:·.:::::::::::··:
38
2.3. System Peripheral
.38
2.3.1. Timer
.38
2.3.2.|NT
39
2.3.3.CCU
39
2.3.4.DMA
,39
2.3.5.PWM,
39
2.4. Display subsystem
39
241. Display engine…,,…
...:::::
39
2.4.2. Display output.....
39
F10600 User Manual( Revision 1.0)
Copyright O2015 Allwinner Technology. Co, Ltd. All Rights Reservec
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2.5. Video Engine
26.| mage Subsystem…
D看看
1,翻看、·着国,着,,,面面,
2.6.1.CS|
4看
40
2.6. 2 CVBS Input
40
2. 7. Audio Subsystem
2.7.1, Audio codec
2.8. System Peripherals
2.8.1.USB2.00TG
41
2.8.2. KEYADC
41
2.8.3.Tl
:::::
41
2.8.4. Digital Audio Interface.....................
2.8.5.UART
41
2.8.6.SP
41
2.8.7.TW|
42
2.8.8.CIR
42
2.8.9,RSB
42
2.8.10.OWA.
42
2.9 Package
42
2.10. System block Diagram
43
Chapter3. System..........................,
44
3.1. Memory Mapping….
45
3.2. CCU
246
3.21 Overy
3.2.2, Feature
F10600 User Manual( Revision 1.0)
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3.2.3. Functionalities Description
3.23.1. System bus…
.:.:::..a...:::::::非
3.23.2 Bus clock tree
47
3.2.4. CCU Register List……
.47
3.2.5. CCU Register Description
48
3.2.5. 1 PLL CPU Control Register
3.2.5.2. PLL AUDIO Control register......................
49
3.2.5.3. PLL VIDEO Control Register
50
3.2.5.4. PLL VE Control Register
51
3.2.5.5. PLL DDR Control Register
3.2.5.6. PLL PERIPH Control Register...............
52
3.2.5.7. CPU Clock Source register
53
3.2.5.8. AHB/APB/HCLKC Configuration Register
54
3.2.5.9. Bus Clock Gating Register O......
.55
3.2.5. 10. Bus Clock Gating Register 1................
55
3. 2.5.11. Bus Clock Gating Register 2
56
3.2.5.12. SDMMCO Clock Register
58
3.2.5.13. SDMMCl Clock Register.
58
325.14. DAUDIO Clock Register……
59
3.2.5.15. OWA Clock Register.........................
59
3.2.5.16. CIR Clock Register
.60
3.2.5.17. USBPHY Clock Register
60
3.2.5. 18 DRAM Gating register.
60
3.2.5. 19 BE Clock Register
61
F10600 User Manual( Revision 1.0)
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3.2.5.20. FE Clock Register
62
3. 2.5.21. TCON Clock Register
62
3.2.5.22. De-interlacer Clock Register
62
3.2.5.23. TVE Clock Register
∴63
3.25.24. TVD Clock Register……
64
3.2.5.25. CSI Clock Register
64
3.2.5.26. VE Clock Register.......
65
3.2.5.27. AUDIO CODEC Clock Register
65
3.2.5.28. AVS Clock Register
.65
3.2.5.29. PLL Stable Time register 0
65
3.2.5.30. PLL Stable Time Register 1...............................................................
65
3.2.5.31. PLL CPU Bias register
66
3.2.5.32. PLL AUDIO Bias Register
66
3.2.5.33. PLL VIDEO Bias Register
66
3.2.5. 34 PLL VE Bias Register
67
3.2.5.35.PLL_ DDR Bias Register…..,…,…,…
67
3.2.5.36.PLL_PER| PH Bias Register……
67
3.2.537.PLL_ CPU Tuning Register.……
68
3.2.5.38. PLL DDR Tuning Register
68
3.2.5.39. PLL AUDIO Pattern Control register........................
69
3.2.5.40. PLL VIDEO Pattern Control Register
.69
3.2.5. 41. PLL DDR Pattern Control Register
3.2.5.42. Bus Software Reset Register O..
3.2.5.43. Bus Software Reset register 1
F10600 User Manual( Revision 1.0)
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3.2.5.44. Bus Software Reset Register 2
3.2.6. Programming guidelines
3.2.6.1.PLL
4看
3.2.6.2.BUS
3.3. Timer
74
3.3 1. Overvi
翻着看
74
3.3.2, Feature
…
74
3.3.3. Functionalities Description..
74
3.3.3.1. Typical Applications
74
3.3.3.2. Functional block Diagram
75
3.3.4.Timer Register List.......................
75
3.3.5. Timer Register Description
3.3.5.1. Timer IRQ Enable Register...
76
3.3.5.2. Timer iRQ Status Register
3.3.5.3. Timer 0 Control Register
3.3.5.4. Timer o Interval value register .................................
3.3.5.5. Timer 0 Current Value Register
3.3.5.6. Timer 1 Control Register....
3.3.5.7. Timer 1 Interval value register
,79
33.58. Timer1 Current Value Register…....…
79
3.3.5.9. T imer 2 Control register
3.3.5.10. Timer 2 Interval value Register
80
3.3.5. 11 Timer 2 Current Value register
3.3.5. 12 AVS Counter Control Register
81
F10600 User Manual( Revision 1.0)
Copyright O2015 Allwinner Technology. Co, Ltd. All Rights Reserved
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3.3.5.13. AVS Counter O Register.
81
335.14. AyS Counter1 Register.,,…,;…,…,…,…
81
3.3.5.15. AVS Counter Divisor Register….,.,,,,…,,…
3.3.5.16. Watchdog irQ Enable Register.………
82
3.3.5.17. Watchdog status
ster
82
3.3.5.18. Watchdog Control Register
83
335.19. Watchdog Configuration Register……,,,…
83
3.3.5.20. Watchdog Mode register....
83
3.3.6. Programming Guidelines
84
3.3.6.1. Timer,,
84
336.2. Watchdog….…
84
3. 4, PWM
85
3.4.1. Overview
85
3.4.2 Feature
85
3.4.3. Functionalities Description
85
3. 1. Functional Block Diagram......
着,着面
85
3.4.4. Operation Principle
86
3. 4.4.1. PWM output pins
86
3.4.5. PWM Register List……
3.4.6. PWM Register Description.....................
3.4.6.1. PWM Control Register.
3.4.6.2. PWM Channel 0 Period Register
88
3.4.6.3. PWM Channel 1 Period register
89
3.5.NTC.
90
F10600 User Manual( Revision 1.0)
Copyright O2015 Allwinner Technology. Co, Ltd. All Rights Reserved
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Revision History
3.5.1. Overview
90
3.5.2, Feature
.:..:.:::::a:::.:::.:.a..:::::.:::::
90
3.5.3. Functionalities Description
90
3.5.3.1. Functional Block Diagram
90
3.5.4.Interrupt source
91
3.5.5. INTC Register List.....................................
3.5.6. INTC Register Description
…
92
3.5.6.1. Interrupt Vector Register.……
92
3.5.6.2. Interrupt base Address register
93
3.5.6.3. NMI Interrupt Control Register
93
3.5.6.4. Interrupt irQ Pending register o
93
3.5.6.5. Interrupt iRQ Pending register 1...............
93
3.5.6.6. Interrupt Enable register o
93
3.5.6.7. Interrupt Enable Register 1.............
93
3.5.6.8. Interrupt Mask register 0
94
3.5.6.9. Interrupt Mask Register 1
.::::
94
3.5.6.10. Interrupt Response Register O.......
94
3.5.6.11. Interrupt Response Register 1
94
3.5.6.12. Interrupt Fast Forcing register 0
94
3.5.6.13. Interrupt Fast Forcing Register 1....................................................................
95
3.5.6. 14 Interrupt Source Priority Register O
95
3.5.6.15. Interrupt Source Priority Register 1...
97
3.5.6.16. Interrupt Source priority register 2
100
3.5.6. 17 Interrupt source priority register 3
102
F10600 User Manual( Revision 1.0)
Copyright O2015 Allwinner Technology. Co, Ltd. All Rights Reserved
Page 10
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