- Ieee Analog Circuit Design -1 .pdf吴重雨，IEEE 2000年

文件名称: - Ieee Analog Circuit Design -1 .pdf

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详细说明：吴重雨，IEEE 2000年讲义，模拟集成电路设计，从原理到应用，适合学习入门3. Roubik Gregorian and gabor c. Temes. Analog mos Integrated Circuits for Signal Processing, John Wiley sons, 1987 4. Technical Papers Final scores: Will be determined by (1)Homework 20% (2)Mid-Term Test 30% (3)Final Exam 30% (4 )Chip Design Project 20%(This Semester) 20%(Next Semester Chip design Schedule Presimulation deadline: Dec. 4. 2000 Layout deadline DeC.25.200(0 Post-Simulation deadline Jan. 8. 2001 Tapeout Lecturer: CHUNG-YUWU(吳重雨) Office: Engineering Building iv, room 537 Email: bywualab ee nctu. edu. tw Web:htto//www.ics.eenctuedu.tw/cvwu Telephone: 03-5712121 Ext 54148 Lecture hours :48 Office Hours: Monday cD Friday gh Others by appointment Teaching Assistants (施育全:p8711837alab. ee.nctu. edu. tw) (周忠昀:p8711581alab. ee nctu. edu. tw) Office: Engineering building iv room 307 Integrated Circuits and Systems Laboratory Telephone: 03-5712121 Ext. 54215 CHUNG-YU WU Chapter 1 Device Physics and SPIce models of Analog mosfets 81-1 Device Physics and Operational Principle B BS P+ N+ N Subtrate Source i Drain HLi- Bulk Pwell P -Subtrate Fig 1 Cross-sectional view of a n-channel mosfet Ds Linear region DSAT VGS Y THO or non saturation rcgion Saturation region Vgs =0 for depletion MOs Increasing GS CVGs=0 for enhancement mos DS g 2 Ips-Vos characteristics of long-channel NMOSFET Linear Region(Non-saturation Region) CHUNG-YU WU Inversion laver D space-charge region P+ N+ p GS Tho(threshold voltage) electron inversion layer(200A)is formed For small vus, it likes an uniform resistor with length Lcff, width W cft? and thickness 200 A Linear Ips-Vps curve IDs=(velocity along channel length).(charges per unit channel length Cox Wer( THO For slightly larger Vps, DS OX ett THO ff Saturation region 1. Pinched-off saturation in long-channel devices s THO P+ N+ DSAT N+ p-W G B P+ we CHUNG-YU WU At Vps = V DSAT GS V THO the channel is pinched off( THO uox W DS THO ff When V s >vsat, the pinched-off point of vsat along the channel is moved toward the source with a distance l from the drain Within L, the electrons can be very quickly swept toward the drain region. Thus the current is not dependent upon the physical behavior of electrons within L 2 GS THO eff C W 2 L S THO eff for L<psat, the charges per unit channel length are increased by a factor of effectively ff DSAT DS eff DSAT GS THO Increasing DS Fig 3 Ips-Vos characteristics of short-channel NMOSFET Ips-VGs characteristics eleni mode enhancement mode THIOD TIIOE 1-5 CHUNG-YU WU Device symbols Enhancement-Mode mosfet Depletion-mode n-channel p- channe」 n-channel B G GO S D OD GO GI GO S S D G S1-1. 1 Threshold Voltage VTH NMOS TH S FB OX MS Cox TH·PMOS Ms: gate material to silicon potential barrier Qss: Surface charge density(C/cm) s: surface potential under strong inversion kT N kT In-A or 2-1 NMOS q n D QB: bulk charge density(C/m) Q NMOS B·PMOS OX.Channel oXIde capacitance per unit area Cov 0.037fF/m2 for Tv 100A 1-6 CHUNG-YU WU ND510 Gate Material ΦMs(V) Q PMOS NMOS PMOS NMOS 0.3 0.85 0.03 0.33 0.88 polysilicon 0.25 0.80 0.0230.273 0.823 p- polysilicon +0.80 +0.30 0.023 0.777 0.277 A for Vn=o, ie zero substrate bias Q si gNA BS Vos:+ forward bias reⅴ erse bias Vri-Vuo+gaMma /sV1 VBs/s 1 VrIo: zero-bias threshold voltage =Vuo+ GaMMa permitivity of si VTH and Vtho: +()for enhancement NMOS(PMOS) GAMMA= l qNA GAMMA: body effect factor Cox Body effect, Substrate bias effect ⅤBs| forward bias TH V reverse bias GAMMA 0.1 to 1.0 GAMMAaVNA To obtain a large enough vTho and a small gamma implantation for threshold voltage adjustment on a small na(nd) sub enhancement implant depletion implant

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