FXLS8962AF Data sheet.pdfNXP 资源来自NXP官网，版权归NXP所有！NX

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详细说明：NXP FXLS8962AF Data sheet.pdf 资源来自NXP官网，版权归NXP所有！NXP Semiconductors FXLS8962AF 3-Axis Low-g Accelerometer 5 Block diagram 32-Sample Output Data Buffer FIFO/LIFO Figure 1. Block Diagram FXLS8962AF AI information provided in this document is sub cct to lccal disclaimers C NXP B.V. 2019. Al rights rosorvcd. Data sheet: technical data Rev. 5.2--16 April 2019 3/99 NXP Semiconductors FXLS8962AF 3-Axis Low-g Accelerometer 6 Pinning information 6.1 Pinning 0 GND BT_MODE2 (9 INTF_SEI SAO! SPI MISO3FXLS8962AF(8INT1/MOT DET SDA/SPL_MOSI/ SPL_DATA 4 7_CS_B/WAKE_UP SCL/SCLK 5 (6 INT2!EXTTRIG/BOOT_OUT Transparent top ew Figure 2. Pin connection diagram 6.2 Pin description Table 2. Pin descriptions Symbol Pin Description Sensor and digital interface supply voltage: 1.71 to 3.6 VDC BT MODE Device boot mode selection GND: Default operating mode enabled Dp: Motion Detection mode enabled SAO/SPI MISO Mode dependent Multifunction serial interface pin INTF SEL=VI SPI MISO: In 4-wire SPI mode this pin functions as the serial data output (Master In SI INTE SEL GND SA0: This pin selects the least significant bit of the device IC slave address SDA/ SPI MOSI/ SPI DATA Mode dependent Multifunction serial interface pin INTF SEL=Vr SPI MOSI: In 4-wire SPI mode this pin functions as the serial data input (Master Out Slave In) SPI DaTa: In 3-wire SPI mode this pin functions as the bidirectional serial data input/output. INTE SEL E GND SDA: This pin functions as the I"C Serial Data input/output SCL /SCLK 5 Mode dependent Multifunction serial interface pin la7 INTE SEL= V SPI serial clock input (3- and 4-wire modes INTE SEL= GND IC serial clock input INT2/ EXT TRIG/BOOT OUT 6 Mode-dependent multifunction 0 pin 2/27 BT MODE=VDD: Open-drain foutput signaling the device boot process has completed. This pin is typically connected to MOT DET in a wired-AND configuration; a pull-up resistor is required BT MODE =GND: Programmable interrupt output pin 2/EXternal measurement trigger input. This pin should be left unconnected if unused in the application circuit FXLS8962AF AI information provided in this document is sub cct to lccal disclaimers C NXP B.V. 2019. Al rights rosorvcd. Data sheet: technical data Rev. 5.2--16 April 2019 4/99 NXP Semiconductors FXLS8962AF 3-Axis Low-g Accelerometer symbol Pin Description SPI CS B/ WAKE UP 7 SPI chip select input, active low/ Hibernate mode Wake-Up pin The WAKE UP function is only available when BT MODE GND INT1/ MOT DET 8 Mode dependent multifunction l/o pin 1. 7 BT MODE= GND: Programmable interrupt output pin 1. This pin should be left unconnected if unused in the application circuit bT MODE VoD: MOT DET multifunction 0 4] The host mcu sets this pin high through a pull-up resistor to enable motion detection, and drives it low for greater than TmoT-HIB ms to disable motion detection and enter Hibernate mode. FXLS8962AF will pulse the line low for TPuLSE-MOT ms after motion is detected. This line may also be used to select the motion detection threshold see Section 12 for more information INTE SEL 9 Device interface mode selection pin VoD: SPl interface mode GND: C interface mode GND Supply return connection. [1 BT MODE state is latched after POR In motion detection mode with BT MODE=VDD, use of HPM or FPM mode is not advised. Only the default LPM mode should be used [2] Under Hibernate mode, pin configuration is High Impedance [3] 3-wire SPl mode may be selected in SENS CONFIG1[SPI M]; 3-wire operation is also possible by directly connecting the SPl MIso and SPl MosI pins together on the PCB 4] An external pull-up resistor is required on this pin when BT MODE= VoD 5 This pin is configurable as either an input or output (push-pull or open-drain/open-source output type), but defaults to a push-pull output after PoR, or after exiting Hibemate mode [6 Under Hibernate mode, pin configuration is High Impedance (when BT MODE= Vou) and CMos Input (when BT MODE= GND [7 Under Hibernate mode, pin configuration is High Impedance(when BT MODE= GND) and CMos Input (when BT MOdE=voI 7 System connections FXLS8962AF connects to a host processor through an ["C or SPl interface. Figure 3 to Figure b show the recommended circuit connections 7.1 Typical application circuits X7R or X5R ceramic capacitors are recommended for Vpp supply decoupling. a 1 uF capacitor in parallel with a 0.1 uF is recommended as a starting point per NXP's EMc test standard. These capacitors should be placed as close to the Vop supply pin as practical. The values of the capacitors can be changed to suit the application ' s EMC performance requirements FXLS8962AF Figure 3. Typical Application Circuit #1-IC mode Notes FXLS8962AF AI information provided in this document is sub cct to lccal disclaimers C NXP B.V. 2019. Al rights rosorvcd. Data sheet: technical data Rev. 5.2--16 April 2019 5/99 NXP Semiconductors FXLS8962AF 3-Axis Low-g Accelerometer Resistors R1 and R2 are not needed if the interrupt output driver type is configured for push-pull operation(default) If either the /NT1 or/NT2 pins are not used in the application, please leave them unconnected The required pull-up resistor values for R3 and R4 are dependent on several factors including the /c clock frequency, bus pull-up voltage, and the total parasitic trace device capacitances. a suggested starting point is 4.7 kn for Standard and Fast ages The external trigger function can be used to initiate a single shot measurement of the XYz acceleration and temperature data. This mode is useful for synchronizing measurements with an external system or for creating user-specific ODRS. The measurement is triggered on the rising edge of the EXT TRIG signal 0.1 HF FXLS8962AF Figure 4. Typical Application Circuit #2-SPI 4-wire mode 10 GND O uF TO 1 uF 9 INTF_SEL BT_ MODE 2 DnC FXLS8962AF 8INT1/MOT_DET 仁>|NT1 SPI DATA SDA/SPI_MOSI/SPI_DATA|4 SPI CS B/WAKE UP SPI CS B/WAKE U SCL/SCLK5 SCLK 6 INT2/EXT_TRIGBOOT_OUT <>INT2/EXT TRIG Figure 5. Typical Application Circuit #3-SPI 3-wire mode (software enabled; SENS CONFIG1[SPI_M]=1) DD DD V 1.0pF 9INTF_SEL BT_MODE 2 R1R2 SAO/SPI MISo 3 FXLS8962AF 8 INT1/MOT_DET SPI DATA SDA/SPI MOSI/SP⊥DATA4 7 SPL_CS_B/AKE_UP SPI_ CS_ B/AKE_ UP SCL/SCLK5 SCLK 6 INT2/EXT_TRIG/BOOT_OUT INT2/EXT TRIG Figure 6. Typical Application Circuit #4-SPI 3-wire mode(hardwired; SENS CONFIG1[SPI M]=X FXLS8962AF AI information provided in this document is sub cct to lccal disclaimers C NXP B.V. 2019. Al rights rosorvcd. Data sheet: technical data Rev. 5.2--16 April 2019 6/99 NXP Semiconductors FXLS8962AF 3-Axis Low-g Accelerometer Notes The external trigger function can be used to trigger a single shot measurement of the XYZ acceleration and temperature data. This mode is useful for synchronizing measurements with an external system or for creating user-specific ODRs. The measurement is triggered on the rising edge of the EXT TRIG signal Resistors R1 and R2 are not needed if the interrupt output driver type is configured for push-pull operation(default). A suggested range for open-drain configuration is 10 kQ2 to 100 kQ If the /NT1 pin, INT2 pin, or both pins are not used in the application, leave the unused pin(s) unconnected The sPl cs B pin also serves as a signal to wake the device from Hibernate mode Refer to section 11.2 and section 11. 4 for more details on 3-wire sPl mode 10 GND INTE SEL 1.0 HF0 1 uF BT_MODE 2 FXLS8962AF 7 SPl_CS_B/WAKE_UP SAO/SPI_MISo3 R2 (optional) SDA/SPL_MOSI/SPL_DATA4 8INT1/MOT_DET X MOT DET SCL/SCLK5 6 INT2/EXT_TRIG/BOOT_OUT (optiona K> BOOT_OUT Figure 7. Typical Application Circuit #5- Motion detection mode(no serial interface) VDD1 10[G 1.0F下0.1μF SP⊥ CS B/WAKE UP 9 INTF_SEL BT MODE 7 SPI_CS_B/AKE_UP DNC FXLS8962AF R1 : R2 (optional) SDA/SPI MOSI/SP! DATA 4 SPI DATA 8 NT1/MOT_DET MOT DET SCLSCLK[5 6 INT2/EXT_TRIG/BOOT_OUT (optional) SCLK BOOT OUT Figure 8. Typical Application Circuit #6 -Motion detection mode with SPl 3-wire interface, software enabled Notes External resistor R2 is not needed if the bOOT oUT and MoT DET pins are tied together (wired AND configuration) A suggested pull-up resistance range is 1 Mn to 2. 5 Mn for both R1 and R2 to minimize the power dissipated in the resistor when the line is pulsed low. When BT MODE is set to Vop(enabling motion detection mode), both the MoT DET and BOOT OUT pins become open-drain output driver types. MOT DET also functions as a CMos input and is used by the host system to power-manage FXLS8962AF When BT_MODE=VoD, the default motion detection parameters are automatically loaded into the device after a POR/BOR event occurs, no configuration via /C or SP/is needed if the default parameters are used in the application FXLS8962AF AI information provided in this document is sub cct to lccal disclaimers C NXP B.V. 2019. Al rights rosorvcd. Data sheet: technical data Rev. 5.2--16 April 2019 7/99 NXP Semiconductors FXLS8962AF 3-Axis Low-g Accelerometer Refer to section 11.2 and section 11. 4 for more details on 3-wire SP/ mode. In motion detection mode with BT_ MODE=VoD, use of HPM or FPM mode is not advised. Only the default LPM mode should be used 7.2 Power supply considerations It is recommended that vod be sourced from a low noise linear supply regulator (LDO) When using a switch mode supply, the recommended minimum voltage is 1.8 V (nominal), providing he ply noise and ripple rejection This ensures that the device will meet its performance specifications while also preventing a BOR/POR event from occurring when operated on a noisy supply rail FXLS8962AF contains a POR generator. This circuit resets the digital logic and restores all register content to the default values shown in table 19 following the application of dD21.71V, or after a soft reset command is issued by setting SENS_ CONFIGl[RSTI 1. Note that the host system must wait for a nominal time period of T Boot1/2 ms after applying VDp21.71V, or after issuing a soft reset command, to allow enough time for FXLS8962AF to complete its internal boot sequence and be ready for communication over the I-C or SPI interfaces. When the bt MOdE pin is low, with INT EN[BOOT DIS] 0, the host system can wait until the active edge of a TPulSe-BOOT1 uS pulse is observed on the INTx pin(determined by INT_PIN_SEL[BOOT_INT2]) indicating completion of the boot sequence. The INT_ STATUs register may also be polled until a successful I C or SPI read indicates the BOoT SRc flag is set. When the BT MODE pin is logic high, the INT2 pin is configured as an open drain output(BOOT_ OUT)that pulses low for TPULSE-BOOT2 ms after the boot sequence completes 8 Sensing direction and output response T。 p VIew Side view Back view Portrait up Pin 1 Xout 0 g Gravity Yout 0 g Zout -1 g Xout o Yout a-1 g Front view Landscape left Zout o g Landscape right ut o g ut1 9 Xout -1 g Xout 1 g Yout 0 g Yout 0 g Zout o Portrait d Zout o g X Xout 0 9 Yout 1 g Zout 0 g Reference frame for acceleration measurement Figure 9. Sensitive axes orientation and output response to t1 g(gravity) stimulus FXLS8962AF AI information provided in this document is sub cct to lccal disclaimers C NXP B.V. 2019. Al rights rosorvcd. Data sheet: technical data Rev. 5.2--16 April 2019 8/99 NXP Semiconductors FXLS8962AF 3-Axis Low-g Accelerometer 9 Mechanical and electrical specifications 9.1 Definitions Sensitivity The accelerometer sensitivity, also known as scale-factor, represents the change in acceleration input corresponding to 1 LSB change in output and is ty pically measured in either mg/LSB or LSB/g Zero-g offset The accelerometer zero-g offset describes the deviation of the sensor output from the ideal values when it is stationary in earth's 1 g gravitational field. With an accelerometer stationary and placed on a level, horizontal surface, the ideal output is 0 g for the x and Y axes, and 1 g for the Z-axis. The deviation of each output from the ideal value called zero-g offset. Offset is, to some extent, a result of stress on the sensor and how well the sensor is leveled when soldered to the board. Therefore, the zero-g offset can change after mounting the sensor onto a printed circuit board or exposing it to extensive mechanical stress For applications that require increased precision, any residual post-board mount offset may be removed using the OF F X/Y/Z registers, or alternatively, in the host application software Self-Test The integrated self-test function can be used to verify correct transducer and signal chain operation without the need to apply an external acceleration stimulus. When the self- test function is activated for each axis, an electrostatic actuation force is applied to the proof mass, simulating a small change in acceleration the device's self-test function is ndependently exercisable for each axis, along with a selectable displacement direction (polarity ). The device need not be static while exercising the self-test function as it is insensitive to any external physical acceleration. Refer to AN5311 for more details on self-test Noise density and RMs integrated noise Noise density is defined as the noise per unit of square root bandwidth and is typically expressed in units of mg/vHz or ug/ Hz for a consumer grade accelerometer Noise is measured with the device held stationary in a 1g field and isolated from environmental noise and mechanical vibration. The RMS noise at a given ODR can be estimated as ND VBW For example, in the +2 g FSR, operating in HPM with an OdR of 400 Hz, the estimated RMS noise would be Nms =280 Hg/Hz*N(400/2)Hz=3.96 mg(-4 LSB) Cross-axis sensitivity Cross-axis sensitivity is the ratio of the measured acceleration for an axis to the input acceleration along each axis orthogonal to the measured axis. Cross-axis sensitivity leads to undesirable nonorthogonality of X, y and z axes in the frame of reference of the assembled device when mapping to other frames of reference Cross-axis sensitivity is expressed as a percentage of the orthogonal input acceleration with six separate FXLS8962AF AI information provided in this document is sub cct to lccal disclaimers C NXP B.V. 2019. Al rights rosorvcd. Data sheet: technical data Rev. 5.2--16 April 2019 9/99 NXP Semiconductors FXLS8962AF 3-Axis Low-g Accelerometer cross-axis sensitivity terms known as Sxy, Sxz, Syx, Syz, Szx and Szy. The cross-axis sensitivity specification represents the maximum of these six terms Output data rate, decimation factor, and power consumption The Output Data Rate(ODR)defines the rate at which acceleration data is output from FXLS8962AF. Depending on the operating mode and OdR that is selected, different decimation factors(oversampling ratios) are applied. The decimated output data is supplied at the ODR rate, even though multiple samples of the sensor data may have been used to calculate this average result In FXLs8962AF's lowest power mode, the decimation factor is always 1, leading to the best power performance at the expense of the poorest noise(resolution) performance In high performance mode, the decimation factor is automatically increased to the maximum possible value for a given ODR, resulting in the best noise(resolution) performance at the expense of the poorest power consumption. In motion detection mode with BT MODE=VDD, use of HPM or FPM mode is not advised. Only the default LPM mode should be used 9.2 Absolute maximum ratings Absolute maximum ratings are the limits the device can be exposed to without damage Functional operation at absolute maximum rating is not guaranteed Although this device contains circuitry to protect against damage due to high static voltage or electrostatic fields, it is advised that normal precautions be taken to avoid application of any voltage higher than the maximum- rated voltage Table 3. Device absolute maximum ratings ymbol Rating Min Max Unit ACCmax 2k Maximum applied acceleration, 0.5 ms duration 2.000 ACC max-10k Maximum applied acceleration, 0. 1 ms duration 10.000 /DDMAX Maximum sensor supply voltage 3.6 ggVV MAX Maximum voltage level applied to any input pin 0.3 VDD+0.3 Operating temperature range -40 +105 °C STG Storage temperature range -40 +125 Table 4. ESD and latch-up-protection characteristics Symbol Rating Min Unit HBM Human Body Mo ±2000 CDM Charged Device Model ±500 LU Latch-up current at T=+105C(per AEC-Q100-004) ±100 m A Caution This device is sensitive to mechanical shock, improper handling can cause permanent damage to the part FXLS8962AF AI information provided in this document is sub cct to lccal disclaimers C NXP B.V. 2019. Al rights rosorvcd. Data sheet: technical data Rev. 5.2--16 April 2019 10/99

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