文件名称:
IntelCPUPowerManagement培训.pdf
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上传时间: 2019-07-20
详细说明：介绍了Intel CPU中Global States,Device States,CPU States,PCIE Link PM State,Sleep StatesAgenda
Introduction
Overview of all power states
Global States
Device States
CPU States
PCle Link PM State
Sleep States
Reset
Backup
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Power Management under ACPI
Advanced Configuration and Power Management Interface
New concepts beyond APM
Fine granularity on CPU clock control
Multiple system sleeping states
Individual device management without H/W traps and timers
Thermal Management
Primary methodology for current power management
Define Power States within the platform
Lx States: Link States(for DMI and PEG)
DX States. Device States
Cx States. CPU States
Sx States Sleep(System) States
MX States ME (AMT)States
Gx States: Global states
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Agenda
Introduction
Overview of all power states
Global States
Device States
CPU States
PCle Link PM States
Sleep States
Reset
Backup
Page 5
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Individual devine can ha in nv and nranneenr
can be in Cx
G1/
G3. no power at all( no battery or the system
GO/SO/C0: F
G02s5
is insufficient supply level to wake)
GO/SO/C1: Ad G1/s4.Dus
GO/S0/C2. St
GO/S0/C3: Stop ClOCK
GO/SO/C4: Stop Clock with lower CPU voltage
Go(Working State)
GO/S0/C5: Stop Clock with partial nower off
System is running
Sleep
Power is on
Hibernate
Wake event
Os initiate
G1(Sleeping State
Power off
No System Traffic
PWR Plug in
AFTERGS EN=0
MCH. ICH and CPU off
G2(Soft Off)
No System Traffic
G3(Mech. Off)
System is off
System is unplugged
Small part of ICH
RIC battery continues
remains on to accept
to supply power to RTC
wake up event.
PWR plug in
AFTERGS EN=1
Paglobal system state
intel?
Agenda
Introduction
Overview of all power states
Global States
Device States
CPU States
PCle Link PM States
Sleep States
Reset
Backup
Page 7
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Device states: Genera
DO Fully-On
o This state is assumed to be the highest level of power consumption
The device is completely active
D1-D2
Optional. Expected to save more power and preserve less device
context than DO. D2 save more power than D1 but the latency is high
D3 Off
Power has been fully removed from the device. The device context is
lost when this state is entered so the os software will reinitialize
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Agenda
Introduction
Overview of all power states
Global States
Device States
CPU States
PCle Link PM States
Sleep States
Reset
Backup
Page 9
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CPU States: General
Co Processor Power state
Normal state. While the processor is in this state, it executes
instructions
C-Cs Processor Power state
Non executing power state.
The deeper the C state, the lower the power consumed by the
processor in that state
Processor power in C1 is higher than the processor power in C4
The deeper the C state, the higher the entry and exit latency
of that state
Entry/exit latency of C4 is higher than that of C1
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