文件名称:
Silicon Processing for the VLSI Era, Vol. 4_
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详细说明：集成电路工艺：Deep-submicron process technology
Describe such deep-submicron process technology and intended to provide semiconductor engineers and researchers with a comprehensive , state-of-the-art reference about these emerging and leading-edge process.CONTENTS
3.2 THE STRUCTURE OF THERMALLY GROWN SIO
And THE PROPERTIES OF THE Si/SiO interface 80
3.2. I The Microscopic Structure of Thermally Grown SiO
3.2.2 The Si/Sio Interface
3.2.2. 1 Interface Trap chs
3.2.2.2 Effect of Interface Traps on IC Characteristics
3.2.2.3 Oxide Trapped Charge
3.2.2.3 Effect of Oxide Trapped Charge on Device Characteristics
3. 3 DIELECTRIC BREAKDOWN IN SILICON DIOXIDE FILMS 90
3.3. 1 Electron Trapping in Silicon Dioxide
3.3.2 The Electric-Field Driven Model of Oxide degradation(E Model)
3.3.3 The Current-Driven Model of Oxide Degradation (1/E Model)
3.3.4 The Hole-Trapping Model that Describes How Holes are Injected
Trapped in Sio2
3.3.5 Comparing the Electric-Field Driven and Current Driven Oxide breakdown Models
3.3.6 Time to Breakdown(TBD)and Charge to Breakdown(Q1
BD
3.4 LEAKAGE CURRENTS IN SiO, FILMS (TUNNELING PHENOMENA) 99
3.4.1 Fowler-Nordheim(FN) Tunneling(tunneling Into Silicon Dioxide)
3.4.2 Direct Tunneling(Tunneling Through Silicon Dioxidc
3.5 MODELS OF THIN OXIDE GROWTH 104
3.6 SINGLE-WAFER TECHNOLOGY OF THIN OXIDE GROWTH 109
3.6.1 Rapid Thermal Oxidation Tools
3.6.2 Wet Rto Processes
3. 7 nitRidEd FluorInated oXides As gate dielectrics 112
3.7. 1 Oxynitridation of Silicon in N,o
3.7.2 Oxynitridation of Oxides in n,o or NO
3.7.3 Fluorinated Gate Oxides
3. 8 PROJECTIONS OF THICKNESS LIMITS OF GATE OXIDES 121
3.8. 1 Minimum Oxide Thickness Due to Defects and Tunneling
3.8.2 Minimum Oxide Thickness: Stress Induced Leakage Current(SILC)
3.8.3 Soft-Breakdown of oxide films
3.8.4 Impact of Polysilicon Depletion
3.8.5 Impact of Process Induced Damage
3.8.6 Summary of Oxide Thickness projections
3.9 MEASURING THIN GATE OXIDES 135
3.10 MANUFACTURING THIN GATE OXIDES 137
C 2002 LATTICE PRESS Sunset Beach Ca All Rights reserved 3.10.1
X
CONTENTS
3.10.1 Process Control Issues of growing Ultra-Thin Gate Oxides
3.10.2 Thin gate Dielectric Stacks Based on silicon dioxide
REFERENCES 139
Chap. 4-HIGH-k DIELECTRICS
145
4.1 HIGH-k DIELECTRICS AS THE GATE DIELECTRIC IN MOSFETS 145
4.1.1 Integrating High-k Dielectrics into MOSFET Structures
4.2 HIGH-K DIELECTRICS AS THE CAPACITOR DIELECTRIC IN DRAMS 150
4.3 HIGH-k DIELECTRICS FOR FERAM APPLICAToNs 154
4.4 TANTALUM PENTOXIDE (Ta,O5) 154
4.4. 1 Tantalum Pentoxide as a dram Capacitor dielectric
4.42 Tantalum Pentoxide as a mosfet gate dielectric
4.5 BARIUM STRONTIUM TITANATE (BST) 162
AS A DRAM CAPACITOR DIELECTRIC
4. 5. 1 Deposition of BsT Films by cvd
4.5.2 Microstructure Effects on the electrical Properties of Bst
4.5.3 BST Integration Issues
4.6 USE OF OTHER HIGH-K MATERIALS AS GATE DIELECTRICS 169
4.6. 1 Atomic Layer Deposition for Depositing Thin High-k Dielectric Films
4.6.2 Aluminum Oxide(al,O3)as a Gate dielectric
4.6.3 Zirconium Oxide(zrO,)as a Gate Dielectric
4.6.4 Hafnium Oxide(HfO,)as a Gate Dielectric
4.6.5 Praseodymium Oxide Pr2O3) as a high-k Gate Dielectric
REFERENCES 177
Chap 5- THE STRUCTURE OF DEEP-SUBMICRON MOSFETS: 181
5.I WELL-FORMATION IN DEEP-SUBMICRON CMOS I&1
5.1. 1 Retrograde-Wells for Deep Submicron CMOS
5.1.2 Process Integration Issues Involving the Use of Retrograde - Wells
5.2 SUPERSTEEP RETROGRADE CHANNEL (SSR) PROFILES 191
5. 2. 1 Fabricating SSR Profiles for Sub-0 1 mm MOSFETs
5. 3 SOURCE/DRAIN ENGINEERING IN DEEP-SUBMICRON CMOS 195
5.3. 1 Parasitic Resistance of Deep-Submicron Source/ Drains
5.3.1. I Physical Meaning of Rac, Rsp, and RsDE
C 2002 LATTICE PRESS Sunset Beach Ca All Rights Reserved
CONTENTS
5.3.1.2 Comparing the resistance of the SDE Region(rsn f SdE) to rsat
5.3.1.3 Parasitic Resistance of the Deep Contact Region of the Drain rco
5.3.2 MOSFETs with Elevated Source/ drains
5.3.3 Shallow-Junction Formation for Deep-Submicron Source/Drains
5.3.3. 1 Ultra-Low-Energy Implants
5.3.3.2 Transient-Enhanced Diffusion
5.3.3. 3 Rapid Thermal annealing of shallow Junctions
5.3.3.4 Dopant Loss for Sub-keV Implants from Self-Sputtering, Out Diffusion,
and surface oxide
5.3. 4 Effect of the Overlap of the sde region and gate edge on
MOSFET Performance
5.3. 5 SDE Junction Lateral Abruptness
5.4 ANTI-PUNCHTHROUGH STRUCTURES IN 219
DEEP-SUBMICRON CMOS
REFERENCES 223
Chap 6-ADVANCED LITHOGRAPHY I: DEEP-SUBMICRON RESISTS 227
6. 1 CHEMICALLY-AMPLIFIED DEEP-UV RESISTS 227
FOR OPTICAL LITHOGRAPHY
6.1.1 248-nm Photoresists
6.1.1. 1 Amine-Contamination of DUV ca resists
6. 1. 1.2 Current State of 248-nm Resist technology
6.1.2193-nm DuV Photoresists
6. 1.2. 1 Problems of 193-nm Resists
6.1.3 157-nm duV Photoresists
6.2 ANTI-REFLECTIVE COATING(ARCs) 244
6.2.1 Organic BaRCs
6.2.2 Inorganic Dielectric BARCS
6.2.3 PVD-Deposited baRCs
6.2.4 BARCS for dual-Damascene applications
6.3 PHOTORESIST PROCESSING SYSTEMS 251
REFERENCES 257
Chap. 7-ADVANCED LITHOGRAPHY ll: OPTICS AND HARDWARE 259
7. 1 EXCIMER LASER DEEP-UV LIGHT SOURCES 259
7. 1.1 KrF Excimer lasers
c 2002 LATTICE PRESS Sunset Beach ca All Rights reserved
CONTENTS
7. 1.2 ArF Excimer Lasers
7.1.3 F, Excimer lasers
7.2 EXPOSURE TOOLS For DUV LITHOGRAPHY 265
7.2. 1 Exposure Tools for 248-nm Lithography
7.2.2 Exposure Tools for 193-nm Lithography
7.2.3 Exposure Tools for 157-nm Lithography
7.2.4 Calcium Fluoride Optical Elements for DUV Lithography
7.2.5 300-mm Lithography tools
7.2.6 Mix-an-Match Lithography
7.3 RESOLUTION ENHANCEMENT TECHNOLOGIES (RETS) 274
7.3.1 Off-Axis Illumination
7.3.2 Optical Proximity Correction(OPC)
7.3.3 Phase Shift Masks(PSm)
7.4 MASK ERROR FACTOR (MEF, or MEEF) 292
7.5 EXTENDING THE LIMITS OF OPTICAL LITHOGRAPHY 296
7.6 NON-OPTICAL (or NEXT GENERATION)
LITHOGRAPHIC TECHNOLOGIES (NGL) 301
7.6. 1 Extreme Ultra-Violet Reflective Projcction Lithography (euv)
7.6.2 Electron Beam Projection Lithography(SCALPEL and PREVAIL
REFERENCES 309
Chap.8-CHEMICAL MECHANICAL POLISHING(CMP)313
8. 1 TERMINOLOGY AND EVOLUTION OF
PLANARIZATION PROCESSES FOR ICS 313
8. 1. 1 Defining the Degree of Planarization
8. 1. 2 The Need for Dielectric Planarization
8. 1.3 Design Rules related to Intermetal Dielectric-Formation
and planarization processes
8. 1. 4 Step-Height Reduction of Underlying Topography
s a technique to alleviate the
Need for planarization
8.1.5 Planarization through Sacrificial-Layer Etchback
8.1.5.1 Sacrificial-Etchback Process Problems
8.2 INTRODUCTION TO CHEMICAL MECHANICAL POLISHING (CMP) 322
8.3 THE TERMINOLOGY USED TO CHARACTERIZE CMP PROCESSES 325
8.3. 1 CMP Removal Rate(rr)
C 2002 LATTICE PRESS Sunset Beach Ca All Rights Reserved
CONTENTS
8.3.2 The Degree of Planarization( DOp)
8.3.3 Within-Die Non-Uniformity (WIDNU)
8.3.4 Within-Wafer Non-Uniformity (WIWNU)
8.3.5 Wafer-to-Wafer Non-Uniformity(WTWND)
8.3.6 Efficiency of Planarization(EOP)
8. 4 THE HISTORY OF CMP 333
8.5 MODELING THE MECHANISMS OF CMP
8.5. 1 The Mechanical Aspects of Silicon Dioxide removal by CMP
(Preston's La
8.5.1. 1 Model of WIWNU Effects in Rotary CMP Tools Based on Preston's Law
8.5.2 Models Which Describe Factors that Impact Oxide rr in CMP
Through the preston Constant
8.5.2. 1 Impact on the Oxide rr from the electrochemical Interactions Between
the Slurry particles and the oxide surface
8.5.2.2 Dependence of Oxide RR in CMP on Dielectric Hardness
8. 5. 3 Models which describe Chemical-Mechanical Phenomena that
Give rise to planarization phenomena associated with cmp of oxides
8.53. 1 Model of the mechanism That Produces planarization of
Steps in Oxide CMP
8.5.3.2 Pattern Dependence of the Planarization Rate in CMP Processes
8.5.4 Metal-CMP Mechanisms
8.6 CMP EQUIPMENT 352
8.6. 1 CMP Polishing Tools
8.6.1. I CMP Polishing Tool Configurations
8.6.1.2 Rotary CMP tools
8.6. 1 3 Orbital CMP tools
8.6.1 4 Linear cmp tools
8.6. 1.5 Fixed Table cmp tools
8.6.1. 300-mm CMP Tools
8.6.2 Wafer-Carriers in CMP Polishing Tools(and the CMP Edge Effect
8.6.2. 1 CMP Edge-Effect
8.6.3 CMP Consumables(Slurries)
8.6.3 1 Slurries for Oxide-CMP
8.6.3.2 Slurries for metal-CMP
8.6.3.3 Multi-Step slurries
8.6.4 Slurry-Distribution Systems
8.6.5 Environmental, Safety, and Handling Issues of CMP Slurries
8.6.6 CMP Consumables(polishing-Pads)
O 2002 LATTICE PRESS Sunset Beach Ca All Rights Reserved
CONTENTS
8.67 Pad-Conditioners
8.6.8 Slurry- Free Pads
8. 6.9 Endpoint-Detection in CMP
8.7 CLEANING ISSUES IN CMP 392
8.7.1 Mechanisms of particle adhesion and removal from surfaces
8.7.1. I Electrical Repulsion of the Particle and the Wafer Surface
8. 7.1.2 Chemically Assisted Particle Remova
8.7.1.3 Mechanically Assisted Particle Removal
8.7.1. 4 Steric Stabilization for Suspending Particles in a Solution
8.7.2 Practical Particle Removal Processes: Brush Scrubbing
8.7.2. 1 Brush Scrubbing to Remove Particles in Post-Oxide-CMP Processes
8.7.2.2 Brush Scrubbing to Remove Particles in Post Metal-CMP Processes
8.7.3 Vibrational Scrubbing to Remove Particles(Megasonic)
8.7.4 Sccondary (or Buff) Polish Procedure as a CMP Cleaning Step
8.7.5 Post-CMP Cleaning of Metallic Contaminants
8.7.6 CMP Cleaning Equipment
8. 8 CMP METROLOGY 407
8. 8. 1 Detection of Defects associated with the CmP Process
8.9 CMP POLISHER TOOL RELIABILITY 411
8.10 CMP SYSTEMS AND PROCESS INTEGRATION 412
8.11 CMP OF VARIOUS MATERIALS 413
8. 11. 1 CMP of Oxide Interlevel Intermetal Dielectrics (ILDs IMDs)
8.11. 2 CMP of Tungsten
8. 11.3 CMP of Copper
8. 11. 4 CMP of aluminum
8. 11.5 CMP of Polysilicon
8.11. 6 CMP of photoresist
8. 11. 7 CMP of Low-k Dielectrics
8.12 MISCELLANEOUS ISSUES CMP 421
8. 12.1 Dishing and erosion
8.12.2 Thickness Non-Uniformity Within a Wafer After CMP
REFERENCES 428
Chap.9-SHALLOW TRENCH ISOLATION (STI)
433
9.1 EARLY SHALLOW TRENCH ISOLATION STRUCTURES 435
9.2 STI-ENABLING PROCESSES 438
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CONTENTS
X
9.3 SHALLOW TRENCH ISOLATION FOR CMOS 439
9.4 DETAILS OF THE PROCESS FLOW TO FORM A
BASELINE SHALLOW-TRENCH-ISOLATION (STD STRUCTURE 446
9.5 ISSUES INVOLVED WITH STI PROCESS INTEGRATION 455
9.5. 1 Issues Involved with etching Trenches for Sti
9.5.2 Corner-Rounding Techniques in STI Structures
9.5.3 Trench-Fill Dielectrics for STi
9.5.4 Dishing problem associated with the Cmp of sti Trench Dielectrics
9. 5.5 Corner Engineering and Its Effects on MOSFET TURN-OFF
Characteristics of moSfets fabricated with Sti
REFERENCES 472
Chap. 10-SILICON-GERMANIUM(Si-Ge)TECHNOLOGY 475
FOR HIGH-PERFORMANCE TELECOMMUNICATIONS ICS
10.1 INTRODUCTION TO HETEROJUNCTION BIPOLAR TRANSISTORS 475
10.2 HETEROJUNCTION BIPOLAR TRANSISTORS WITH
LARGE-BANDGAP EMITTERS
480
10.3 HETEROJUNCTION BIPOLAR TRANSISTORS WITH
SMALLER BANDGAP BASE REGIONS (Si-Ge BASE) 482
10.4 PROCESS TECHNOLOGY FOR FABRICATING SI-GE HBTS 484
10.5 PROCESS INTEGRATION ISSUES
foR BICMOS TECHNOLOGY WITH SI-Ge hbt 486
10.6 HIGH-QUALITY SI-GE EPITAXIAL FILM GROWTH ON PATTERNED WAFERS 491
10.7 THERMAL STABILITY PROCESS INTEGRATION ISSUES 492
10.8 COMPATIBILITY WITH ION IMPLANTATION PROCESSES 492
10.9 COMPATIBILITY WITH THERMAL OXIDATION PROCESSES 493
10.10 VERTICAL SCALING OF Si GC HBTs 493
10.11 BASE-DURING-GATE AND BASE-AFTER-GATE
BICMOS PROCESS FLOWS
495
10.12 EXAMPLES OF THE MODULAR INTEGRATION OF
Si-Ge hbts into a BiCMOS PROCESS FLOW
497
REFERENCES 499
Chap. 11-SILICON-ON-INSULATOR(SOD)TECHNOLOGY 501
11.1 WHAT IS SILICON-ON-INSULATOR (SOD? 501
o 2002 LATTICE PRESS Sunset Beach CA All Rights Reserved
XVI
CONTENTS
11. 1. 1 Isolation Issues in CMOs in Bulk Silicon
1. 1.2 Isolation in SOI CMOS
IL2 THE END OF THE ROAD FOR BULK CMOS SCENARIO
PREDICTED BY THE 1999 INTERNATIONAL TECHNOLOGY
ROADMAP FOR SEMICONDUCTORS
505
11. 2. I Source/Drain Junction Scaling
11.2.2 Dopant Activation in Shallow Source/Drain Junctions
11. 2.3 Doping Profile Abruptness in Shallow Source/Drain Junctions
11.3 WHY SOI 510
11.3. 1 The Path of Using SOI May Allow Extension of the ITRS Roadmap
11.4 HISTORY OF SILICON-ON-INSULATOR (SOI) TECHNOLOGY 516
11.5 SILICON-ON-INSULATOR DEVICES 518
11. 5.1 Partially-Depleted Thin SOI MOSFETS(PD-SOls)
11.5.2 Fully-Depleted Thin SOI MOSFETS (FD-SOls
1.5.3 Process Technologies Used to Fabricate Fully-Depleted SOI Devices
11.5.3. 1 FD-SOI: Thinning Si-SOI Surface Layer by Thermal Oxidation
11.5.3.2 FD-SOI Fabrication by LoCoS Recess of the mosfet Channel region
11. 6 FABRICATION TECHNOLOGIES USED TO PRODUCE SOI-
STARTING-WAFERS
11.6.1 Silicon-on-Sapphire(SOs)
11.6.2 SoI by Separation by Implanted Oxygen(SIMOX)
11.6.2. 1 High-Dose SIMOX
11.6.2.2 LOW-Dose SImoX
11.6.3 Wafer Bonding
11.6.3.I Bond and Etch-back SOI (BESOn
11.6.3.2 Hydrogen-Implantation-Induced Layer Splitting to Create SOI Substrates
(SMART-CU
11.6.3.3 NANOCLEAVE Wafer Bonding SOI
11.6.3.4 ELTRAN Wafer Bonded SOI
II.7 LATERAL ISOLATION IN SOI 550
11. 8 SOI PRODUCT EVOLUTION 556
11.9 PROBLEMS ASSOCIATED WITH SOI 559
11.9. 1 Floating Body Effects in Partially-Depleted SOI MOSFETS
11.9.1. I Kink Effect in Partially Depleted SOI NMOSFET
11.9.1. 2 Transient In effects
11.9.1.3 Effect of Building Partially Depleted SOI MOSFETS Without Body Contacts
11.9.2 Short-Channel Effects in SOI MOSFETs
c 2002 LATTICE PRESS Sunset Beach Ca All Rights Reserved
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