ADS1018IDGST 高压采集芯片.PDF外部高压 ADC采样芯片 datasheet .lEX

文件名称: ADS1018IDGST 高压采集芯片.PDF

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详细说明：外部高压 ADC采样芯片 datasheet .lEXAS INSTRUMENTS ADS1018 vww.ti.com.cn ZHCSAJ4C-NOVEMBER 2012-REVISED NOVEMBER 2015 Changes from Revision A( December 2012 )to Revision B Page Changed bit 1 to NoPo in Table 5 19 · Changed noP bit description in Table5: changed bits2:o] to bits[2:1] and changed NoP to NOP[1:0]…………20 Changes from Original(November 2012)to Revision A Page 已删除器件图片. 已更新首页图片 Copyright C 2012-2015, Texas Instruments Incorporated EXAS INSTRUMENTS ADS1018 ZHCSAJ4C-NOVEMbER 2012-REVISED NOVEMBER 2015 www.ti.com.cn 5 Device Comparison Table MAXIMUM SAMPLE INPUT CHANNELS DEVICE ESOLUTION RATE Differential PGA INTERFACE SPECIAL (Bits) SPs) FEATURES (Single-Ended ADS1118 16 860 2(4) Yes SPI Temperature sensor ADS1018 3300 2(4 Yes SPI Temperature sensor ADS1115 16 860 2(4) Yes Comparator ADS1114 1(1) Comparato ADS1113 1(1) None ADS1015 3300 2(4) Yes Comparator ADS1014 12 3300 Ye 2C Comparator ADS1013 3300 1(1) None 6 Pin Configuration and Functions RUG Package DGS Package 10-Pin X2QFN 10-Pin VSSOP Top view Top view DIN 10 9/DOUT SCLK 10D|N SCLK DRDY CS2 9/DOUT/ CS 8 VDD DRDY 8 VDD GND 7|A|N3 AINO AlN AINO 4 6|A|N2 A|N15 6A|N2 AIN1 Pin functions PIN TYPE DESCRIPTION No NAME SCLK igital input Serial clock input Digital input Chip select; active low. Connect to gnd if not used GND Suppl Ground 4 AINO Analog input Analog input 0. Leave unconnected or tie to VDD if not 5 AIN1 Analog input Analog input 1. Leave unconnected or tie to VDD if not 6 AlN Analog input Analog input 2. Leave unconnected or tie to VDD if not used ain Analog input Analog input 3. Leave unconnected or tie to Dd if not used 8 VDD Supply Power supply. Connect a0.1-HF power-supply decoupling capacitor to GND 9 DOUT/DRDY Digital output Serial data output combined with data ready; active low DIN Digital input Serial data input Copyright 2012-2015, Texas Instruments Incorporated lEXAS INSTRUMENTS ADS1018 vww.ti.com.cn ZHCSAJ4C-NOVEMBER 2012-REVISED NOVEMBER 2015 7 Specifications 7.1 Absolute Maximum Ratings over operating ambient temperature range(unless otherwise noted)) MIN MAX UNIT Power-supply voltage Vdd to GND 03 55 Analog input voltage AINO, AIN1AIN2, AIN3 GND-0.3 VDD+0.3 Digital input voltage DIN. DOUT/DRDY SCLK, CS GND-0.3 VDD +0.3 Input current, continuous Any pin except power supply pins mA Junction T 150 Temperature Storage, T. 60 150 (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability 7.2 ESD Ratings VALUE UNIT (ESD) Electrostatic Human-body model(HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±4000 discharge Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1000 (1)JEDEC document JEP 155 states that 500-V HBM allows safe manufacturing with a standard EsD control process 2)JedEC document JEP157 states that 250-V cdm allows safe manufacturing with a standard esd control process 7. 3 Recommended Operating Conditions over operating ambient temperature range(unless otherwise noted) MIN NOM MAX UNIT POWER SUPPLY VDD Power supply VdD to GND 2 55 V ANALOG INPUTS(1) FSR Full-scale input voltage( 2) IN=V(AINP)-VIAINNI See Table 1 M AINp and aiNn denote the selected positve and negative inputs. AIN x denotes one of the four available anglo irae(2 V(AINx) Absolute input voltage GND VDD DIGITAL INPUTS Input voltage GND VDD TEMPERATURE Operating ambient temperature -40 applied to this device 7. 4 Thermal Information ADS1018 THERMAL METRIC (1) DGS (VSSOP) RUG (X2QFN) UNIT 10 PINS 10 PINS Junction-to-ambient thermal resistance 186.8 245.2 C ReJC(top Junction-to-case(top) thermal resistance 693 eJB Junction -to-board thermal resistance 108.4 °c Junction-to-top characterization parameter 2.7 8.2 °CN Junction-to-board characterization parameter 106.5 170.8 CN ReJC(bot) Junction-to-case(bottom) thermal resistance N/A N/A (1) For more information about traditional and new thermal metrics, see the semiconductor and /C Package Thermal Metrics application report, SPRA953 Copyright C 2012-2015, Texas Instruments Incorporated EXAS INSTRUMENTS ADS1018 ZHCSAJ4C-NOVEMbER 2012-REVISED NOVEMBER 2015 www.ti.com.cn 7 5 Electrical characteristics Maximum and minimum specifications apply from ta=40c to +125 C. Typical specifications are at ta=25c All specifications are at VDd=3.3 V and FSR=+2.048V(unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ANALOG INPUTS FsR=±6.144V(1) FSR=±4096V(1).FSR=±2.048V Common-mode input impedance 863 MO FSR=±1.024V FSR=±0.512V,FsR=±0.256V 100 FsR=±6,144V(1 22 FSR=±4096V(1) 15 Differential input impedance FsR=±2048V 4.9 FsR=±1.024V 2.4 FSR=±0.512V,FSR=±0.256V 710 kQ SYSTEM PERFORMANCE Resolution(no missing codes) 12 Bits Data rate 128.250.490,920.1600.2400.3300 SPS Data rate variation all data rates 10% 10% Integral nonlinearity DR=128 SPS FSR=+2.048 V(2) 0.5 LSB FSR=+2.048 differential inputs ±0.5 Offset error LSB FSR=+2.048 V, single-ended inputs ±0.25 Offset drift FSR=±2.048V 0.002 LSB/°C Offset channel match Match between any two inputs 0.25 LSB Gain error (3) FSR=±2048V,TA=25℃C 0.05 0.25% FSR=±0.256V 7 Gain drift (3)(4) FSR=±2048V 5 40 ppm/C FSR=±6.144V(1) Gain match(3) Match between any two gains 0.02% 0.1% Gain channel match Match between any two inputs 0.05% 0.1% TEMPERATURE SENSOR Temperature range 40 125 Temperature resolution 0.125 °CsB A=0°cto70°c 0.25 ±1 Accuracy TA=-40。cto+125°c 0.5 versus supply 0.125 ±1°CN (1) This parameter expresses the full-scale range of the ADC scaling. No more than VDD+0.3V or 5.5V(whichever is smaller) must be applied to this device (2) Best-fit INL; covers 99% of full-scale 3)Includes all errors from onboard PGa and voltage reference (4) Maximum value specified by characterization Copyright 2012-2015, Texas Instruments Incorporated lEXAS INSTRUMENTS ADS1018 vww.ti.com.cn ZHCSAJ4C-NOVEMBER 2012-REVISED NOVEMBER 2015 Electrical Characteristics(continued) Maximum and minimum specifications apply from TA =-40C to +125 C. Typical specifications are at TA= 25C All specifications are at VDd=3. 3V and FSr=+2.048 V(unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAXUNIT DIGITAL INPUTS/OUTPUTS High-level input voltage 0.7 VDD VDD V LOW-level input voltage GND 0.2 VDD VoH High-level output voltage OH =1 mA 0.8VDD LoW-level output voltage loL =1 mA GND 0.2 VDD Input leakage, high VIH=5.5V 10 A Input leakage, low VIL GND 10 10 A POWER SUPPLY Power-down,TA=25°C 0.5 2 Power-down IvDp Supply current Operating 50 200 300 VDD=5V 0.9 Power dissipation DD=3.3V 0.5 VDD=2V 0.3 Copyright C 2012-2015, Texas Instruments Incorporated EXAS INSTRUMENTS ADS1018 ZHCSAJ4C-NOVEMbER 2012-REVISED NOVEMBER 2015 www.ti.com.cn 7.6 Timing Requirements: Serial Interface over operating ambient temperature range and Vdd=2 V to 5.5 V(unless otherwise noted) MIN MAX UNIT tcsc Delay time, CS falling edge to first sclK rising edge 1) 100 sccs Delay time, final sCLK falling edge to CS rising edge ns Pulse duration, Cs high 200 SCLK SCLK period 250 ns tspwh Pulse duration, SCLK high 100 ns 100 ns Pulse duration scLK low(2) 28 ms Setup time, DIN valid before SCLK falling edg DIHD Hold time, DIN valid after SCLK falling edge 50 ns tDaHD Hold time, SCLK rising edge to dOUT invalid ns (1) Cs can be tied low permanently in case the serial bus is not shared with any other device (2) Holding SCLK low longer than 28 ms resets the SPI interface 7.7 Switching Characteristics: Serial Interface over operating ambient temperature range(unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Propagation time tcsDod CS falling ed dOuT driven DOUT load= 20 pF 100 kQ to GND 100 ns Propagation delay time tDoPD SCLK rising edge to valid new DOUT DOUT load= 20 pF l 100 k to GND 50 Propagation delay time tcsDoz CS rising edge to DOUT high impedance DOUT load= 20 pF l 100 k to GND 100 ns CS F CSH ts CLK PWH tscs SPW OHD IDOFD DOUT Figure 1. Serial Interface Timing Copyright 2012-2015, Texas Instruments Incorporated lEXAS INSTRUMENTS ADS1018 vww.ti.com.cn ZHCSAJ4C-NOVEMBER 2012-REVISED NOVEMBER 2015 7. 8 Typical Characteristics at TA=25C, Vdd=3.3V, and FSR=+2.048 V(unless otherwise noted) 00 4.5 250 VDD=5V x200 3.5 VDD=2 V 3150 VDD=2V VDD=3.3V 云25 VDD=3.3V 515 0.5 VDD=5V 0-20020406080100120140 40-20020406080100120140 Temperature(°C) Temperature (C) Figure 2. Operating Current vs Temperature Figure 3. Power-Down Current vs Temperature 60 FSR==4.096V FSR=±1.024V --FsR=_2.048V FSR=±0.512V VDD=5V VDD=2V VDD=4V D=3 10 DD=5V VDD=2V 250 10 6080100120140 40-200 Temperature(C) Temperature(C) Figure 4. Single-Ended Offset Voltage vs Temperature Figure 5. Differential offset Voltage vs Temperature 0.05 FSR=±0.256 Average Temperature Error 0.8 erage±3sg 0.6 Average±6sgma 0.03 FSR=±0.512V 0.4 点0.01 0.2 山 FSR=±1.024V,±2.048V, ±4096√1).and±6.144y1) 0.01 0.02 0.04 40-20020406080100120140 40-20020406080100120 Temperature(C) Temperature(°C) Figure 6. Gain Error vs Temperature Figure 7. Temperature Sensor Error vs Temperature (1)This parameter expresses the full-scale range of the ADC scaling. In no event should more than VDD+0.3v be applied to this device Copyright C 2012-2015, Texas Instruments Incorporated EXAS INSTRUMENTS ADS1018 ZHCSAJ4C-NOVEMbER 2012-REVISED NOVEMBER 2015 www.ti.com.cn 8 Detailed description 8.1 Overview The ADS1018 is a very small, low-power, noise-free, 12-bit, delta-sigma(42)analog-to-digital converter(ADC) The ADS1018 consists of a A2 ADC core with adjustable gain, an internal voltage reference, a clock oscillator and an SPL. This device is also a highly linear and accurate temperature sensor. All of these features are intended to reduce required external circuitry and improve performance. The Functional Block Diagram section shows the ADs1018 functional block diagram The aDs1018 ADC core measures a differential signal, VIN, that is the difference of V(AINP) and V(AINN). The converter core consists of a differential, switched-capacitor A2 modulator followed by a digital filter This architecture results in a very strong attenuation in any common-mode signals Input signals are compared to the internal voltage reference. The digital filter receives a high-speed bitstream from the modulator and outputs a code proportional to the input voltage The Ads1018 has two available conversion modes: single-shot and continuous- conversion In single-shot mode the adc performs one conversion of the input signal upon request and stores the value to an internal conversion register. The device then enters a power-down state. This mode is intended to provide significant power savings in systems that require only periodic conversions or when there are long idle periods between conversions. In continuous-conversion mode, the ADC automatically begins a conversion of the input signal as soon as the previous conversion is completed. The rate of continuous conversion is equal to the programmed data rate Data can be read at any time and always reflect the most recently completed conversion 8.2 Functional Block Diagram VDD Device Mux AINO SCLK 12-Bt△∑ PGA ADC Peripheral Q DIN Interface Q DOUT/DRDY Temperature ain tmt t Copyright 2012-2015, Texas Instruments Incorporated

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