ads8588s 中文datasheet ADS8588S在在单单电电源源上上具具有有

文件名称: ads8588s 中文datasheet

所属分类: 硬件开发

开发工具:

文件大小: 2mb

下载次数: 0

上传时间: 2019-07-03

提供者: nono****

下载 (2mb)

不能下载？报告错误

详细说明：ADS8588S在在单单电电源源上上具具有有双双极极性性输输入入的的 ADS8588S 16 位位、、高高速速 8 通通道道、、同同步步采采样样 ADClEXAS INSTRUMENTS ADS85885 vww.ti.com.cn ZHCSFSBA-DECEMBER 2016-REVISED APRIL 2017 修订历史记录( continued) Changed conversion to conversion results in first sentence of third paragraph in Serial Data Read section 42 Changed x-axis of curves DC Histogram for OSR2 to DC Histogram for OSR64 45 Changed 2nd-order to 3rd-order in 8-Channel dAQ for Power Automation Using the ADS8588S figure........ 47 Changed 2nd-order to 3rd-order in Input RC Low-Pass Filter figure 48 Deleted PSRR Across Frequency(Without Decapacitor) figure from Power Supply Recommendations section 51 Changed PSRR Across Frequency(With Decapacitor) figure 51 Copyright C 2016-2017, Texas Instruments Incorporated EXAS INSTRUMENTS ADS8588S ZHCSFS8A-DECEMBER 2016-REVISED APRIL 2017 www.ti.com.cn 5 Device Family Comparison Table PRODUCT RESOLUTION (Bits) CHANNELS SAMPLE RATE (KSPS) ADS8588S 16 8, single-ended 200 ADS8586S 6, single-ended 250 ADS8584S 16 4, single-ended 330 ADS8578S 14 8, single-ended 200 6 Pin Configuration and Functions PM Package: ADS8588S 64-Pin LQFP Top view 口 8a9 GBB这885品寻 AVDD L AVDD AGND 2 AGND OSo 46 REFGND OS1 REFCAPB OS2 REFCAPA PARISER/BYTE SEL [I6 REFGND STBY 42 REFIN/REFOUT RANGE AGND CONVSTA 40[Ac GND CONVSTB 39 REGCAP2 RESET AVDD RD/SCLK rLrLrrLr AVDD BUSY 114 AGND FRSTDATA 115 REFSEL DBO 16 DB15/BYTE SEL R而N8886888两8 酉曾舀舀 0n n 0 m Not to scale g Copyright o 2016-2017, Texas Instruments Incorporated lEXAS INSTRUMENTS ADS85885 vww.ti.com.cn ZHCSFSBA-DECEMBER 2016-REVISED APRIL 2017 Pin Functions PIN TYPE(1)DESCRIPTION NAME NO AGND 2,26,35,40,41,47 Analog ground pin AIN 1GND PAA Analog input channel 1: negative input AIN 1P Analog input channel 1: positive input AIN 2GND Analog input channel 2: negative input AIN 2P 51 A Analog input channel 2: positive input AIN 3GND Analog input channel 3: negative input AIn 3P Al Analog input channel 3: positive input AIN 4GND 56 Al Analog input channel 4: negative input AIN 4P Al Analog input channel 4: positive inout AIN 5GND Al Analog input channel 5: negative input AIN 5P A Analog input channel 5: positive input AIN 6GND A Analog input channel 6: negative input AIN 6P Analog input channel 6: positive input AIN 7GND Analog input channel 7: negative input AIN 7P 61 Analog input channel 7: positive input AIN 8GND Analog input channel 8: negative input Ain 8P Analog input channel 8: positive input AVDD 1,37,38.48 P Analog supply pins. Decouple these pins to the closest AGND pins ee the Power Supply recommendations section BUSY 14 Active high digital output indicating ongoing conversion (see the BUsY(Output) section) CONVSTA 9 D Active high logic input to control start of conversion for first half count of device input channels(see the CONVSTA, CONVSTB (Input) section) CONVSTB Active high logic input to control start of conversion for second half count of device input channels(see the CoNvsTA, CONVsTB (Input) section) D Active low logic input chip-select signal (see the Cs (Input) section) DBO Do Data output DBO(LSB) in parallel interface mode(see the DBrs: 0) section) DB 1 DO Data output DB1 in parallel interface mode(see the DB 6.0 se DB2 18 DO Data output DB2 in parallel interface mode(see the db[6: 0 section) DB3 DO Data output DB3 in parallel interface mode(see the DB/6: 0 section) DB4 Data output DB4 in parallel interface mode(see the dB/6. 0 section) DB5 21 Data output DB5 in parallel interface mode(see the DB/6: 0 section) DB6 Do Data output DB6 in parallel interface mode(see the DB(6: 0) section) Multi-function logic output pin(see the DB7/DOUTA section DB7/DOUTA this pin is data output DB7 in parallel and parallel byte interface mode this pin is a data output pin in serial interface mode Multi-function logic output pin(see the DB8/DOUTB section) DB8/DOUTB Do this pin is data output DB8 in parallel interface mode this pin is a data output pin in serial interface mode DB9 DO Data output DB9 in parallel interface mode(see the DB(13: 9 section DB10 Data output DB10 in parallel interface mode (see the dB/13: 9 section) DB11 do Data output DB11 in parallel interface mode(see the DB/13: 9]section) DB12 Data output DB 12 in parallel interface mode(see the DB/13: 9 section) DB13 31 DO Data output DB13 in parallel interface mode(see the DB/13: 9) section) Multi-function logic input or output pin(see the DB14/HBEN section) DB14/HBEN DIo this pin is data output DB14 in parallel interface mode this pin is a control input pin for byte selection( high or low) in parallel byte interface mode Multi-function logic input or output pin (see the DB15/BYTE SEL section) DB15/BYTE SEL DIo this pin is data output DB15(MSB )in parallel interface mode this pin is an active high control input pin to enable parallel byte interface mode DVDD P Digital supply pin; decouple with aGND on pin 26 ERSTDATA 15 Do Active high digital output indicating data read back from channel 1 of the device(see the FRSTDATA(Output) section) (1)Al =analog input; AO =analog output; Alo = analog input/output; DI =digital input; DO =digital output; DIo= digital input/output; P power supply; and nc= no connect Copyright C 2016-2017, Texas Instruments Incorporated EXAS INSTRUMENTS ADS8588S ZHCSFS8A-DECEMBER 2016-REVISED APRIL 2017 www.ti.com.cn Pin Functions(continued) PIN TYPE(1) DESCRIPTION NAME NO OSo 3 D Oversampling mode control pin see the Oversampling Mode of operation section OS1 Oversampling mode control pin (see the Oversampling Mode of Operation section) OS2 5 D Oversampling mode control pin see the Oversampling Mode of Operation section) PARSER/EYTE SEL DI Logic input pin to select between parallel, serial, or parallel byte interface mode(see the Data Read Operation section Multi-function logic input pin(see the RANGE(Input section) RANGE 8 DI when STBY pin is high, this pin selects the input range of the device (+10 V or +5 V);when STBY pin is low, this pin selects between the standby and shutdown modes Multi-function logic input pin(see the RD/SCLK(Input)section) RD/SCL his pin is an active-low ready input pin in parallel and parallel byte interfac this pin is a clock input pin in serial interface mode REFCAPA Ao Reference amplifier output pins. This pin must be shorted to REF CAPB and decoupled to AGND using a low ESR, 10-uF ceramic capacitor REFCAPB 45 AO Reference amplifier output pins. This pin must be shorted to REFCAPA and decoupled to AGND using a low ESR, 10-HF ceramic capacitor REFGND REFIN/REFOUT on pin 42 using a 10-F capacitor analog GNd plane and decoupled with Reference GND pin. This pin must be shorted to the This pin acts as an internal reference output when REFSEL is high REFINREFOUT 42 Alo this pin functions as input pin for the external reference when REFSEL is low decouple with REFGND on pin 43 using a 10-HF capacitor REFSEL D Active high logic input to enable the internal reference (see the REFSEL(Input) section REGCAP1 Ao Output pin 1 for the internal voltage regulator,; decouple separately to AGND using a 1-uF capacite REGCAP2 AO Output pin 2 for the internal voltage regulator; decouple separately to AGND using a 1-HF capacitor RESET 11 D Active high logic input to reset the device digital logic (see the RESET(Input) section) STBY 7 D Active low logic input to enter the device into one of the two power-down modes: standby or shutdown(see the Power-Down Modes section) 7 Specifications 7.1 Absolute Maximum Ratings at<.C(unless otherwise noted)(1) MIN MAX UNIT AVDD to aGnD 0.3 DVDD to dgND 0.3 7.0 aGnd to dGND 0.3 0.3 V Analog input voltage to AGND(2) 15 Digital input to DGND 0.3 DVDD+0.3 REFIN to agnd 0.3 AVDD +0.3 Input current to any pin except supplies(2) -10 10 MA Operating Temperature Junction t 150 Storage, I stg 65 150 (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability (2) Transient currents of up to 100 ma do not cause SCR latch-up Copyright o 2016-2017, Texas Instruments Incorporated lEXAS INSTRUMENTS ADS85885 vww.ti.com.cn ZHCSFSBA-DECEMBER 2016-REVISED APRIL 2017 7.2 ESD Ratings VALUE UNIT Human-body model (HBM),per All pins except analog inputs ±2000 ANSUESDAJEDEC S-001(1) Analog input pins only ±7000 (ESD Electrostatic discharge Charged-device model (CDM), per JEDEC specification JESD22-C101 All pins ±500 (1)JEDEC document JEP 155 states that 500-V HBM allows safe manufacturing with a standard EsD control process (2) JEdEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process 7.3 Recommended Operating Conditions over operating free-air temperature range(unless otherwise noted) MIN NOM MAX UNIT AVDD Analog supply voltage 4.75 5 5.25 DVDD Digital supply voltage 2.3 3.3 AVDD 7, 4 Thermal Information ADs85885 THERMAL METRIC(1) PM(LQFP) UNIT 64 PINS Junction -to-ambient thermal resistance 46.0 °C AJC(top) Junction-to-case(top) thermal resistance 7.8 C/W B Junction -to-board thermal resistance 20.1 C/W YJT Junction -to-top characterization parameter 0.3 YJB Junction-to-board characterization parameter 19.6 °c Junction-to-case(bottom)thermal resistance NIA °c (1)For more information about traditional and new thermal metrics, see the Semiconductor and /C Package Thermal Metrics application Copyright C 2016-2017, Texas Instruments Incorporated EXAS INSTRUMENTS ADS8588S ZHCSFS8A-DECEMBER 2016-REVISED APRIL 2017 www.ti.com.cn 7 5 Electrical characteristics minimum and maximum specifications are at ta=-40C to +125 C, aVdd=4.75V to 5.25 V; typical specifications are atTa 25C: AVDD=5V, dVdd=3V, VREF =2.5V(internal), and samPLe =200 ksPS (unless otherwise noted) TEST PARAMETER TEST CONDITIONS MIN TYP MAX UNIT LEVEL(1) ANALOG INPUTS Full-scale input span (2) RANGE pin 1 (AIN_nP to AIN_ nGND) RANGE Pin =0 Operating input range. RANGE pin 1 10 AIN nP positive input RANGE pin =0 AIN nGND negative input ge Operating input rar All input ranges 3 0 0.3 B Input impedance At TA =25"C 0.85 1 1.15M B Input impedance drift All input ranges 25 25 ppm/CB Input leakage current With voltage at AIN nP= ViN, all input ranges OVIN-2)/RIN A A SYSTEM PERFORMANCE Bits NMC No missing codes Bits Differential nonlinearity All input ranges 0.5 ±0.35 0.5 LSB(3) Integral nonlinearity (4) All input ranges 1.5 1.5 LSB All input TA=-40°cto ranges, +85°C -64 external Gain errol Ta=-40°cto reference +125°C 96 LSB A All input ranges, intemal reference Input range=±10V A Gain error matching external and internal reference (channel-to-channel LSB Input range=土5V, external and internal reference 12 All input ranges 14 B external reference Gain error temperature drift ppm/C All input intemal reference ±10 B Input range=±10V -1.8 ±0.15 1.8 B Offset errol Input range=±5V 18 ±0.15 8 B Offset error matching All input ranges 0.3 2.4mV B Offset error temperature drift All input ranges n/C B SAMPLING DYNAMICS Acquisition time Maximum throughput rate per channel without latency All eight channels included 200KSPS (1)Test Levels: (A) Tested at final test. Overtemperature limits are set by characterization and simulation. (B)Limits set by characterization and simulation, across temperature range. ( C)Typical value only for information, provided by design simulation (2)Ideal input span, does not include gain or offset error. (3)LSB=least significant bit (4)This parameter is the endpoint INL, not best-fit (5) Gain error is calculated after adjusting for offset error, which implies that positive full-scale error negative full-scale error gain error Copyright o 2016-2017, Texas Instruments Incorporated lEXAS INSTRUMENTS ADS85885 vww.ti.com.cn ZHCSFSBA-DECEMBER 2016-REVISED APRIL 2017 Electrical Characteristics(continued) minimum and maximum specifications are at Ta=-40C to+125 C, Avdd=4.75V to 5.25 V; typical specifications are at Ta 25C: AVDD=5V, DVDd=3V, VREF =2.5V(internal), and sample 200 kSPS (unless otherwise noted) PARAMETER TEST CONDITIONS TEST MIN TYP MAX UNIT LEVEL(1) DYNAMIC CHARACTERISTICS Signal-to-noise ratio nput range=±10V 91 92.7 no oversampling 0.5 dBFS at 1 kHz) Input range=±5V 90.4 92.2 A Signal-to-noise ratio nput range=±10V 955 964 oversampling 16x (VIN -0.5 dBFS at 130 Hz) Input range=±5V 94.4 95.5 A Total harmonic distortion (6) THD (IN -0.5 dBFS at 1 kHz) All input ranges 114 95 B Signal-to-noise distortion ratio Input range=±10V 90.7 92.7 A SINAD no oversampling (VIN.5 dBFS at 1 kHz) 90.2 92.1 Signal-to-noise +distortion ratio Input range=±10V 96.4 A SINADOsR oversampling =16X IN0.5 dBFS at 130 Hz) Input range=±5V 94 SFDR Spurious-free dynamic range All input ranges -118 0.5 dBFS at 1 kHz) Crosstalk isolation AtTN=25°C, input range=±10V B BW(3 dB) -3 dB KHz AtTA=25°C Small-signal input range=±5V 16 bandwidth AtTA=25°C, B input range=±10V 14 BW(.1 dB) 0.1dB kHz At TA=25C input range=±5V 9.5 nput range=±10V Group delay nput range=±5V INTERNAL REFERENCE OUTPUT (REFSEL =1) REF Voltage on the REFIN/REFOUT pin At TA=25C configured as output 2.4975 2.5 2.5025 A nternal reference temperature drift 7.5 B Decoupling capacitor on REFIN- REFOUT) REFIN/REFOUT19 F B Reference voltage to the ADC R=FCAP) (on the REFCAPA, REFCAPB pin) At TA=25'C 3.996 4.0 4.004 A Reference buffer output impedance 0.5 C Reference buffer output temperature ppm/ C B Decoupling capacitor on REFCAPA, REFCAP) REFCAPB UF B Turn-on time (REFCAP )=10uF, C(REFIN REFOUD= 10 uF ms B EXTERNAL REFERENCE INPUT(REFSEL= O External reference voltage on REFIO V REFIO EX configured as input 2475 2.5 2.525 Reference input impedance 100 Mo BCC Reference input capacitance 10 (6) Calculated on the first nine harmonics of the input frequency (7) Isolation crosstalk is measured by applying a full-scale sinusoidal signal up to 160 kHz to a channel, not selected in the multiplexing sequence, and measuring the effect on the output of any selected channel 8) Does not include the variation in voltage resulting from solder shift effects 9)Recommended to use an X/R-grade, 0603-size ceramic capacitor for optimum performance(see the layout Guidelines section) Copyright C 2016-2017, Texas Instruments Incorporated EXAS INSTRUMENTS ADS8588S ZHCSFS8A-DECEMBER 2016-REVISED APRIL 2017 www.ti.com.cn Electrical Characteristics(continued) minimum and maximum specifications are at Ta=-40C to+125 C, Avdd=4.75V to 5.25 V; typical specifications are at Ta 25C: AVDD=5V, DVDd=3V, VREF =2.5V(internal), and sample 200 kSPS (unless otherwise noted) PARAMETER TEST CONDITIONS TEST MIN TYP MAX UNIT LEVEL(1) POWER-SUPPLY REQUIREMENTS AVDD Analog power-supply volt Analog suppl 4.75 5 5.25 DVDD Digital power-supply voltage Digital supply 2.3 3.3 AVDD A For ADS8588S AVDD=5 V 17.7 4.0 Analog supply current intemal reference AVDD DYN MA (operational) For ads8588S AVDD=5V fs 200 ks 24.0 A exte For ADs8588S AVDD=5 V 12.4 17.0 A Analog supply current static For Ads8588S AVDD=5V external reference 12.0 17.0 A device not converting At avdd=5v device in STDBY mode 4.2 5.5 AVDD STDB AVDD supply intemal reference STANDBY current At avdd=5v device in STDBY mode 3.8 5.5 external reference At avdd=5v device in AVDD supply PWR DN. internal or VDD PWR power-down current 0.2 external reference TA=-40°Cto+85C For ads8588S DVDD DYN Digital supply current DVDD=3.3 V 0.15 0.3mA A fs 200 kSPS At AVdd=5. device in STDBY VDD STDBY DVDD supply STANDBY current 0.05 1.5 A VDD PWR DVDD supply power-cown current At avdd=5. device in PWR DN mode 0.05 1.5 A DIGITAL INPUTS (CMOS) Digital high input level DVDD>23 V 7X DVDD DVDD +0.3 Digital low input level DVDD>2.3V 0.3x DVDD Input leakage current 100 Input pin capacitance DIGITAL OUTPUTS (CMOS Digital high output voltage logic level lo=100-HA source .8×DVDD DVDDV Digital low output voltage logic level Io =100-HA sink 0 0.2×DVDD V Floating state leakage current Only for SDO A Internal pin capacitance 5 F A TEMPERATURE RANGE Operating free-air temperature 125C A Copyright o 2016-2017, Texas Instruments Incorporated

(系统自动生成,下载前可以参看下载内容)