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详细说明：64-ia-32-architectures-software-developer-system-programming-manualCONTEN
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PAGE
CHAPTER T
ABOUT THIS MANUAL
INTEL 64 AND IA-32 PROCESSORS COVERED IN THIS MANUAL
OVERVIEW OF THE SYSTEM PROGRAMMING GUIDE
NOTATIONAL CONVENTIONS
1.3.1
Bit and Byte Order..,..
3.2
Reserved Bits and Software Compatibility
1-6
13.3
Instruction Operands
3.4
xadecimal and binary numbe
13.5
Segmented Addressing
36
Syntax for CPUID, CR, and Msr values
1-8
3.7
Exceptions
RELATED LITERATURE
CHAPTER 2
SYSTEM ARCHITECTURE OVERVIEW
2.1 OVERVIEW OF THE SYSTEM-LEVEL ARCHITECTURE
2.1.1
Global and local descriptor tables
2-3
2.1.1.1
Global and Local Descriptor Tables in IA-32e Mode
1着
,2-4
2.1.2
System Segments, Segment Descriptors, and Gates
4
2.1.2.
Gates in lA-32e Mode
2-4
2.1.3
Task-State Segments and Task Gates
2.1.3.
Task-State Segments in lA- 32e Mode
2.14
Interrupt and Exception handling
2.14
Interrupt and Exception Handling lA-32e Mode
2.1.5
Memory Management
2-6
2.1.5
Memory Management in IA-32e Mode........
2-6
2.1.6
System Registers.............
2.1.6
System Registers in iA-32e Mode.
2.1.7
Other System Resources
22
MODES OF OPERATION
22.1
Extended Feature Enable Register.
23 SYSTEM FLAGS AND FIELDS IN THE EFLAGS REGISTER
2.3.1 System Flags and Fields in IA-32e Mode
24 MEMORY-MANAGEMENT REGISTERS
24.1
Global Descriptor Table Register (GDTR)
24.2
Local Descriptor Table Register(LDTR)
24.3
IDTR Interrupt Descriptor Table register
2-12
244
Task Register (TR)
2-13
25
CONTROL REGISTERS
2-13
251
CPUID Qualification of Control Register Flags
2.6 EXTENDED CONTROL REGISTERS (INCLUDING XCRO
2-19
7 PROTECTION KEY RIGHTS REGISTER(PKRU
....:::..:::.::
2-20
2.8 SYSTEM INSTRUCTION SUMMARY
2-20
28.1
oading and storing System Registers
,,,2-22
28.2
Verifying of Access Privileges
-22
28.3
Loading and storing Debug Registers
2-23
284
Invalidating Caches and TlBs
2-23
28.5
Controlling the Processor
2-24
28.6
Reading performance- Monitoring and Time-Stamp Counters
2-24
286.1
Reading Counters in 64-Bit Mode
∴2-25
28.7
Reading and writing model-Specific Registers
,2-25
28.7.1
Reading and writing model-Specific registers in 64-Bit Mode
2-25
288
Enabling processor Extended states...,,,,,.
2-25
ol.3AⅢ
CONTENTS
PAGE
ChAPTER 3
PROTECTED-MODE MEMORY MANAGEMENT
3.1
MEMORY MANAGEMENT OVERVIEW
3.2
USING SEGMENTS
,3-2
3.2.
Basic Flat model
3.2.2
Protected flat model
重1着
1鲁
3.2.3
Multi-Segment Model
::::
3.24
Segmentation in IA-32e Mode
3-5
3.25
Paging and segmentation
3-5
PHYSICAL ADDRESS SPACE73-6
33.1
Intel64 Processors and Physical Address space
3-6
34
LOGICAL AND LINEAR ADDRESSES
3-6
34.1
Logical Address Translation in IA-32e Mode
...:::::.::.:::
3.4.2
Segment Selectors.................
.,··,·,··
34.3
Segment Registers...,...
1能
3-8
344
Segment Loading Instructions in IA-32e Mo
34.5
Segment Descriptors
3-9
3.4.5.1
Code-and Data-Segment Descriptor T ypes
,3-12
3.5
SYSTEM DESCRIPTOR TYPES
3.5.1
Segment descriptor Tables
.3-14
3.52
Segment descriptor Tables in iA-32e Mode
.3-16
CHAPTER 4
PAGING
PAGING MODES AND CONTROL BITS
4.1.1
Three Paging modes
着1
1
4.1.2
Paging -Mode Enabling
4-3
4.1.3
Paging- Mode Modifiers
,4-4
4.14
Enumeration of Paging Features by CPUID
.:.:.:::..:::....:::........:.
4-5
4.2
HIERARCHICAL PAGING STRUCTURES: AN OVERVIEW
重11,111111
,4-6
43
32-BIT PAGING
4-7
44
PAE PAGING
n1,_1
4-13
4.4.1
PDPTE Registers
4-13
4.4.2
Linear-Address Translation with PAE Paging
∴.4-14
4.5
lA-32E PAGING
4-19
46
ACCESS RIGHTS
4-28
46.1
Determination of Access rights
,4-29
46.2
Protection Keys
11411111,普,11着着
4-31
4.7 PAGE-FAULT EXCEPTIONS
4-31
4.8 ACCESSED AND DIRTY FLAGS
4-33
9
PAGING AND MEMORY TYPING
1·着1,
4-34
49.1
Paging and Memory typing When the pat is not Supported (Pentium Pro and Pentium ll Processors)
,4-34
492
Paging and Memory typing when the pat is Supported (pentium lll and more recent Processor Families)..... 4-34
4.9.3 Caching Paging-Related Information about Memory Typing
4-35
4.10 CACHING TRANSLATION INFORMATION
4-35
4.10.1
Process-Context identifiers(PClDs)
4-35
4.10.2
Translation Lookaside Buffers (tlbs)
4-36
4.102.1
Page Numbers, Page Frames, and page offsets
:::.::.1:.:..::.:.1::::::
4-36
4.102.2
Caching Translations in TLBS.......
,4-36
4.102.3
Details of tlb use
4-37
4.10.2.4
Global Pages
重1,1,1
n_重1,t
,4-37
4.103
Paging-Structure Caches
4-38
4.10.3.1
Caches for Paging Structures.
11首
11
4-38
4.10.32
Using the Paging-Structure Caches to Translate Linear Addresses
4-40
4.10.33
Multiple Cached Entries for a Single Paging-Structure Entry
4-40
4.10.4 Invalidation of TLBs and Paging-Structure Caches
4-41
4.104
Operations that Invalidate tLBs and Paging-Structure Caches
4-41
4.10.4.2
Recommended invalidation
4-43
4.104.3
Optional Invalidation
4-44
4.1044
Delayed Invalidation
4-44
4.105
Propagation of Paging-structure Changes to Multiple Processors
4-45
4.11 INTERACTIONS WITH VIRTUAL-MACHINE EXTENSIONS ( UMX
4-46
4.11.1 VMX Transitions
4-46
∨o.3A
CONTENTS
PAGE
4.11.2 VMX Support for Address Translation................
,,4-46
4.12 USING PAGING FOR VIRTUAL MEMORY
4-47
4.13 MAPPING SEGMENTS TO PAGES
4-47
CHAPTER 5
PROTECTION
5.1 ENABLING AND DISABLING SEGMENT AND PAGE PROTECTION
5.2
FIELDS AND FLAGS USED FOR SEGMENT-LEVEL AND
PAGE-LEVEL PROTECTION
111
5-2
5.2.1
Code- Segment Descriptor in 64-bit
5-3
53
LIMIT CHECKING
Ini
5-4
53.1
Limit Checking in 64-bit Mode
5-5
54
TYPE CHECKING
.1...:
..:::
着,1
5-5
54.1
Null Segment selector Checking
54.1.1
NULL Segment Checking in 64-bit Mode
5-6
55
PRIVILEGE LEVELS
.::::::.
5.6 PRIVILEGE LEVEL CHECKING WHEN ACCESSING DATA SEGMENTS
11D1n
5-8
56.1
Accessing Data in Code Segments
5.7 PRIVILEGE LEVEL CHECKING WHEN LOADING THE SS REGISTER
...5-10
5.8 PRIVILEGE LEVEL CHECKING WHEN TRANSFERRING PROGRAM CONTROL BETWEEN CODE SEGMENTS
5-10
58.1
Direct Calls or Jumps to Code segments
.5-10
58.1.1
Accessing Nonconforming Code Segments
58.1.2
Accessing Conforming Code segments
5-12
58.2
Gate Descriptors
583
Call gates
,1着,,,
,,5-13
58.3.1
A-32e Mode call gates
1,
5-14
584
Accessing a code segment through a call gate
5-15
58.5
Stack Switching.……
5.8.5.1 Stack Switching in 64-bit Mode
1,D1着
58.6
Returning from a Called Procedure. ........,.,.,.,.
1着1
111重
5-20
58.7
Pertorming Fast Calls to system Procedures with the
SYSENTER and syseXit instructions
.5-20
58.7.1
SYSENTER and syseXit instructions in lA-32e Mode
588
Fast System Calls in 64-Bit Mode
.5-22
59
PRIVILEGED INSTRUCTIONS
,5-23
5.10 POINTER VALIDATION
5-24
5.10.1 Checking Access Rights(LAR Instruction)
5-24
5. 10.2 Checking Read/Write Rights (vERR and VERw Instructions
5.10.3 Checking That the pointer Offset Is Within Limits(LSL Instruction
.5-25
5.10.4 Checking Caller Access Privileges (ARPL Instruction
5.10.5 Checking Alignment...
5.11 PAGE-LEVEL PROTECTION
.:...:::
5-27
5.11.1
Page-Protection Flags.....
5-28
5.11.2
Restricting Addressable Domain
5.11.3
5-28
5.11.4 Combining Protection of Both Levels of page Tables
.5-28
5.11.5 Overrides to Page Protection
11L
11,,11
着着
5.12 COMBINING PAGE AND SEGMENT PROTECTION
5-29
5.13 PAGE-LEVEL PROTECTION AND EXECUTE-DISABLE BIT
,,5-30
5.13.1
Detecting and enabling the execute-Disable capability
5-30
5.13.2 Execute-Disable Page Protection
着着着
5.13.3 Reserved Bit Checking
5.13.4
Exception Handling ..,...,...
5-32
CHAPTER 6
INTERRUPT AND EXCEPTION HANDLING
6.1
INTERRUPT AND EXCEPTION OVERVIEW
6.2 EXCEPTION AND INTERRUPT VECTORS
6
63
SOURCES OF INTERRUPTS
6-2
6.3.1
External Interrupt
63.2
Maskable Hardware Interrupts
633
Software-Generated Interrupts
...:::::::::.:.:::
..:::
着,1
6-4
VoL 3A y
CONTENTS
PAGE
64 SOURCES OF EXCEPTIONS
着着1自D1着1重D1
,6-4
64.
Program-Error Exceptions
11411111着111着着1
6-4
6.42
Software-Generated Exceptions
6-4
64.3
Machine-Check Exceptions
6-4
65
EXCEPTION CLASSIFICATIONS
6.7 NONMASKABLE INTERRUPT(NMI)
6-6
67.1
Handling multiple nmis
,,6-6
68
ENABLING AND DISABLING INTERRUPTS
6-6
68.
Masking maskable Hardware Interrupts
6-6
682
Masking Instruction Breakpoints.........
着1
着1
683
Masking Exceptions and Interrupts When Switching Stacks
6-7
6.9 PRIORITY AMONG SIMUL TANEOUS EXCEPTIONS AND INTERRUPTS
6-8
6.10 INTERRUPT DESCRIPTOR TABLE (IDT)
,.6-9
PTOR
6.12 EXCEP TION AND INTERRUPT HANDLING
,6-10
6-11
6.12.1
Exception -or Interrupt-Handler procedures
,,6-11
6.12.1.1
Protection of EXception-and Interrupt-Handler Procedures
6.12.1.2
Flag Usage By Exception -or Interrupt-Handler Procedure
...6-14
6.122
Interrupt Tasks
11
6-14
6.13 ERROR CODE
6-15
6.14 EXCEPTION AND INTERRUPT HANDLING IN 64-BIT MODI
6-16
6.14.1
64-Bit Mode idt
6-16
6.14.2 64-Bit Mode stack frame
.:.::.::.a
6-17
6. 14.3 RET in IA-32e Mode
6-18
6.144
Stack Switching in IA-32e Mode
6-18
6.145
Interrupt Stack Table
,6-19
6.15 EXCEP TION AND INTERRUPT REFERENCE
6-19
Interrupt o-Divide Error Exception(#DE
6-20
Interrupt 1-Debug Exception ( #DB)
Interrupt 2-NM Interrupt
6-22
Interrupt 3-Breakpoint Exception(#BP)....,...,.,..
重重
∴.6-23
Interrupt 4-Overflow Exception #
,6-24
Interrupt 5-BOUND Range Exceeded Exception#BR).,...,..,...
:..:
1.11着
.6-25
Interrupt 6-Invalid Opcode Exception ( #UD)
6-26
Interrupt 7-Device Not Available Exception (#NM)
.6-27
terrupt 8-Double Fault Exception(#DF)
6-28
Interrupt 9--Coprocessor segment overrun
::.::
6-30
Interrupt 10-Invalid TSS Exception(# Ts
重111111111着
,6-31
Interrupt 11-Segment Not Present(#
6-34
Interrupt 12-Stack Fault Exception(#ss)
6-36
Interrupt 13-General Protection Exception #GP)
6-37
Interrupt 14Page-Fault Exception (#PF)
6-40
upt 16-X87 FPU Floating-Point Error(#MF)
6-43
Interrupt 17-Alignment Check Exception (#AC
6-45
terrupt 18-Machine-Check Exception(#MC)
6-47
terrupt 19-SIMD Floating-Point EXception(#XM)
6-48
Interrupt 20-Virtualization Exception( #VE
6-50
interrupts 32 to 255-User Defined Interrupts
1着
6-51
CHAPTER 7
TASK MANAGEMENT
TASK MANAGEMENT OVERVIEW
7.1.1
ask Structure
7.1.2
ask state
Executing a T ask
着1
7.2 TASK MANAGEMENT DATA STRUCTURES
7.2.1
Task-state Segment (Tss
7.22
TSS Descriptor
72.3
SS Descriptor in 64-bit mode.
11鲁着1重
724
Task Register..,.....
::::·.
vi Vol. 3A
CONTENTS
PAGE
72.5
Task-Gate Descriptor.............
7-8
73 TASK SWITCHING
1着廉111,4,,1,,111111111411日,,1日11着着
,,7-9
74 TASK LINKING
7-12
74.1
Use of Busy Flag To Prevent Recursive Task Switching
7-13
74.2
Moditying T ask Linkages
,,7-13
TASK ADDRESS SPACE
7-14
75.1
Mapping Tasks to the Linear and Physical Address spaces
..7-14
752
Task Logical Address space
7-15
7.6 16-BIT TASK-STATE SEGMENT (TSS)
∴7-15
7,7
TASK MANAGEMENT IN 64-BIT MODEA7-16
ChaPTER 8
MULTIPLE-PROCESSOR MANAGEMENT
8.1
LOCKED ATOMIC OPERATIONS
8-1
8.1.1
Guaranteed Atomic Operations
8.1.2
Bu
1..:.....:·:·::
8-3
8.1.2.1
Automatic Locking.....................
11D1n
8-3
8.12.2
Sottware Controlled Bus Locking
8-3
8.1.3
Handling selt-and cross Modifying code
8-4
8.14
Effects of a loCK Operation on Internal processor caches
8-5
8.2
MEMORY ORDERING
8-5
82.1
Memory Ordering in the Intel Pentium and Intel486 Processors
8-6
822
Memory Order ing in P6 and More Recent processor Families
8-6
823
Examples Illustrating the Memory-Ordering Principles
8-7
823.1
Assumptions, Terminology, and Notation
8-8
82.3.2
Neither Loads Nor stores Are reordered with like Operations
8-9
823.3
Stores are Not reordered with earlier loads
8-9
82.34
oads may be reordered with earlier stores to Different Locations
8-9
82.3.5
Intra-Processor Forwarding ls Allowed
82.3.5
Stores Are Transitively Visible
8-10
8.2.3.7
Stores are seen in a Consistent Order by other Processors
8-11
823.8
ocked instructions have a total order
8.2.39
Loads and stores are not reordered with locked instructions
8-12
8.24
Fast-String Operation and out-of-Order stores
8-12
824.1
Memory-Ordering Model for String Operations on Write-Back (WB)Memory
:·:
8-13
8242
Examples Illustrating Memory-Ordering Principles for String Operations
,8-13
825
Strengthening or Weakening the memory-Ordering Model
8-15
8.3 SERIALIZING INSTRUCTIONS
8-17
8.4 MULTIPLE-PROCESSOR (MP)INITIALIZATION
8-18
84.1
BSP and Ap Processors
8-18
842
MP Initialization Protocol requirements and restrictions
8-19
84.3
MP Initialization Protocol Algorithm for MP Systems
8-19
844
MP Initialization Example.....
,8-20
844.1
Typical BSP Initialization Sequence
844.2
Typical AP Initialization Sequence
..8-22
84.5
Identifying Logical Processors in an MP System
.8-23
8.5 NTEL HYPER-THREADING TECHNOLOGY AND INTELB MULTI-CORE TECHNOLOGY
,,8-24
8.6 DETECTING HARDWARE MULTI-THREADING SUPPORT AND TOPOLOGY
,8-24
86.1
Initializing Processors Supporting Hyper-Threading Technology
8-25
862
Initializing multi-Core Processors
8-25
Handling Interrupts on an IA32 Processor Supporting Hardware Multi-Threading,,,,UIti-Threading
8.6.3 Executing Multiple Threads on an Intel64 or IA-32 Processor Supporting Hardware Mi
8-26
864
8-26
8.7 NTEL HYPER-THREADING TECHNOLOGY ARCHITECTURE
8.7
State of the logical Processors∴………
..8-27
37,2
APIC Functionality............
,8-28
8.7,3
Memory T ype Range Registers MTRR)
8-28
8.74
Page Attribute Table(Pat)
8-28
8.7.5
Machine check architecture
8-28
87.6
Debug registers and Extensions
8-29
87.7
Performance monitor ing Counters
着1
1
878
lA32 MISC ENABLE MSR
879
Memory ordering
8-29
8.7.10 Serializing Instructions
1着
,,,,8-29
8.7. 11 Microcode Update resources...........
11
日1,,
,8-29
Vol 3a vil
CONTENTS
PAGE
87.12
Self Modifying Code.
..::.
8-30
8.7.13 Implementation-Specific Intel HT Technology Facilities
11着,着,1
8-30
8.7.13.1
Processor caches
8-30
87.13.2
Processor Translation Lookaside Buffers(TlBs)
8-30
87.13.3
Thermal monitor
87.134
External Signal Compatibility
..8-31
8. 8 MULTI-CORE ARCHITECTURE
8-31
88.1
Logical Processor Support..,...
8-32
88.2
Memory Type Range Registers (MTRR
∴,8-32
883
Performance monitoring counters
,8-32
884
lA32 MISC ENABLE MSR
着1着
8-32
885
Microcode update resources
8-32
89
PROGRAMMING CONSIDERATIONS FOR HARDWARE MULTI-THREADING CAPABLE PROCESSORS
8-33
89.1
Hierarchical Mapping of Shared Resources
重1
8-33
892
Hierarchical Mapping of CPUid Extended Topology Leaf.
8-34
893
Hierarchical id of Logical Processors in an mP System
835
893.1
Hierarchical id of logical processors with x2APIC ID
8-37
894
Algorithm for Three-Level Mappings of APIC_ID
895
Identifying Topological Relationships in a MP System
8-42
8.10 MANAGEMENT OF IDLE AND BLOCKED CONDITIONS
8-46
8.10.1
HLT Instruction
8-46
8.10.2 PAUSE Iostruction
8-46
8.103
Detecting support MoNiToR/MWAIT Instruction
8-46
8.104
MONITOR/MWAIT Instruction
8-47
8.10.5
Monitor/Mwait Address range determination
:::
,,8-48
8.106
Required Operating System Support
,848
8.10.6
Use the PaUsE Instruction in Spin-Wait Loops
1着着DD着D,,1·D1着1着11着
,8-49
8.1062
Potential Usage of MONITOR/MWAIT in Co ldle Loops.
,8-49
8.106.3
Halt ldle logical processors
8-50
8.1064
Potential Usage of MoNITOR/MWAlT in Cl Idle Loops
8-5
8.1065
Guidelines for Scheduling Threads on Logical Processors Sharing EXecution Resources
8.106.6
Eliminate Execution-Based Timing Loops
.8-52
8.10.6.7
Place Locks and Semaphores in Aligned, 128-Byte Blocks of Memory
∴8-52
8.11 MP INITIALIZATION FOR P6 FAMILY PROCESSORS
,8-52
8.11.1 Overview of the mp Initialization Process For P6 Family processors
,,8-52
8.112
MP Initialization Protocol Algorithm
∴8-53
8.11.2.1
Error Detection and handling during the mp initialization Protocol
,8-54
CHAPTER 9
PROCESSOR MANAGEMENT AND INITIALIZATION
9.1
INITIALIZATION OVERVIEW
9.1.1
Processor state After reset
,9-2
9.1.2 Processor Built-In Self-Test(BIST)
9.1.3
Model and stepping Intormation
9-5
9.14
First instruction executed
9-5
92
X87 FPU INITIALIZATION
1
9-5
92.1
Configuring the x87 FPU Environment ...,....
seting the processor for x87「 PU Software Emulation∵
1着
922
9-6
93
CACHE ENABLING
94
MODEL-SPECIFIC REGISTERS (MSRS
9.5 MEMORY TYPE RANGE REGISTERS MTRRS)............................
9-8
96
INITIALIZING SSE/SSE2/SSE3/SSSB3 EXTENSIONS
9-8
97
SOFTWARE INITIALIZATION FOR REAL-ADDRESS MODE OPERATION
9-8
97
Real-Address mode idt
,9-8
972
NMI Interrupt Handling
∴9-9
9.8 SOFT WARE INITIALIZATION FOR PROTECTED-MODE OPERATION
9-9
98.1
Protected-Mode system Data Structures
9-9
98.2
Initializing Protected-Mode exceptions and Interrupts
.9-10
983
Initializing Paging ...,..,.,
∴,9-10
984
Initializing multitasking
,,9-10
985
Initializing IA-32e Mode
98.5.1
IA-32e Mode System Data Structures
9-11
9852
IA-32e Mode Interrupts and Exceptions.,.........
...:::::::::.:.::
9-12
9853
64-bit Mode and Compatibility Mode operation
11,,1
.9-12
ⅷii∨ol.3A
CONTENTS
PAGE
9854
Switching Out of IA-32e Mode Operation
9.9 MODE SWITCHING
1着,1日14,
11411111着1D1着111111.着,、1着
∴9-13
99.1
Switching to Protected Mode
9-13
992
Switching back to Real-Address mode
9-14
9.10 NITIALIZATION AND MODE SWITCHING EXAMPLE
,9-14
9. 10.1 Assembler Usage
b
9.10.2
STARTUP. ASM Listing
9-16
9.10.3
MAINASM Source code
∴,9-25
9.104
Supporting files...,,.
9-25
9.11 MICROCODE UPDATE FACILITIES
11,,1鲁
,9-27
Microcode Update
1
着1
1
∴9-28
9.11.2 Optional Extended Signature Table
9-31
911.3
Processor ldentification
9-32
9.11.4
Platform ldentification
9-32
9.11.5 Microcode Update Checksum............,...
9-33
9. 11.6 Microcode Update Loader
,9-34
9.11.6.1
Hard resets in Update Loading
,,9-35
9.11.62
Update in a Multiprocessor System
.9-35
9.11.63
Update in a System Supporting Intel Hyper-Threading Technology
.
..9-35
9.11.64
Update in a system Supporting dual-Core Technology
....:::::
,9-35
9.1165
Update loader Enhancements.....
9-35
9. 11.7 Update Signature and verification
9-36
9.11.7.1
Determining the signature
9-36
9.11.7,2
Authenticating the Update
9-37
9.11.8 Optional Processor Microcode Update Specifications
9-37
9.118.1
Responsibilities of the blos
9-38
91182
Responsibilities of the calling Program
9-39
91183
Microcode Update functions
9-42
9.11.84
INT 15H-based Interface
9-42
9.11.85
Function ooh-presence test
9-42
9.11.85
Function 01H-Wwrite Microcode Update Data
..9-43
9.11.8.7
Function 02H-Microcode Update control
9-46
91188
Function 03H-Read Microcode Update Data.
9-47
9.1189
Return codes
,,,,,,9-48
CHAPTER 10
ADVANCED PROGRAMMABLE
INTERRUPT CONTROLLER (APIC)
10.1 LOCAL AND IO APIC OVERVIEW
10-1
10.2 SYSTEM BUS VS APIC BUS
10-4
10.3 THE INTEL 82489DX EXTERNAL APIC THE APIC THE XAPIC AND THE XZAPIC
10-4
10.4 LOCAL APIC
1
,10-4
10.4.1 The Local aPiC Block Diagram
着1
..10-4
10.4.2 Presence of the local apic
10-7
10.4.3 Enabling or Disabling the local aPlc
10-8
1044
ocal Apic status and location
,1着1111着B
10-8
10.4.5 Relocating the Local APIC Registers
,,,10-9
1046
Local aPic id
1111
:.:.:::::::.::.:::::::
10-9
104.7
Local apic state
10-10
104.7,1
Local APIC State After Power-Up or Reset
10-10
104.7.2
Local apic state After It has been software disabled
..10-10
104.7.3
Local APlC State After an INIT Reset (wait-for-SIPI State)
.10-10
104.7.4
Local apic state after lt receives an nit-Deassert iP
10-11
1048
Local aPlc version Register.
10-11
10.5 HANDLING LOCAL INTERRUPTS
10-11
10.5.1 Local vector table
10-12
10.5.2 Valid Interrupt Vectors
10-14
10.5.3 Error Handling
,,10-14
10.5.4 APIC Timer
1,,1,1着
∴10-16
105.4.1
TSC-Deadline mode
10-17
105.5
Local Interrupt Acceptance
10-18
10.6 SSUING INTERPROCESSOR INTERRUPTS
,,10-18
10.6.1
Interrupt Command Register(ICR)
10-18
voL.3Aⅸx
CONTENTS
PAGE
106.2
Determining IPl Destination
1,,11鲁1
着1,L自,,1D1
10-22
106.2.
Physical Destination Mode
1着,,,11“4,111D11“4D111自,11
着着1,1
,10-22
1062.2
Logical Destination Mode
10-23
10623
Broadcast/Self delivery mode
10-24
106.24
Lowest Priority Delivery Mode
,,,10-24
10.63
IPI Delivery and Acceptance
..10-25
10.7 SYSTEM AND APIC BUS ARBITRATION
10-25
10.8 HANDLING INTERRUPTS
,10-26
10.8.1 Interrupt Handling wi th the pentium 4 and Intel Xeon Processors
10-26
108.2
Interrupt Handling with the p6 Family and pentium Processors
,,10-27
10.8.3 Interrupt, Task, and Processor Priority
着1
1
10-28
083.1
Task and processor priorities
10-28
10.8.4 Interrupt Acceptance for Fixed Interrupts
10-29
10.8.5 Signaling Interrupt Servicing Completion
10-30
108.6
Task Priority in IA-32e Mode
:.:..::..:::
.10-31
08.6.1
Interaction of task priorities between cr8 and apic
10-31
10.9 SPURIOUS INTERRUPT
10-32
10.10 APIC BUS MESSAGE PASSING MECHANISM AND
PROTOCOL (P6 FAMILY, PENTIUM PROCESSORS)
.10-32
10.10.1 Bus Message Formats
10-33
10.11 MESSAGE SIGNALLED INTERRUPTS
10-34
10.11. 1 Message Address register Format.
10-34
10.11.2 Message Data Register Format....,,.....,,.
10-35
10.12 EXTENDED XAPIC (X2APIC)
0-36
10.12.1 Detecting and Enabling X2APIC Mode
..:
∴10-36
10.12.1.1 Instructions to Access APIC Registers
10-37
10.12.12
X2APlC Register Address space....,..,..,.
10-37
10.12.13
Reserved Bit Checking
1着自11着首着1
10-39
10.12. 2 X2APIC Register Availability
,,10-40
10.123 MSR Access in x2APIC Mode
10-40
10.12. 4 VM-EXit Controls for MSRs and X2APIC Registers
...10-40
10.125 x2APIC State transitions
.10-4
10.125.1
x2APIC States
,,,10-41
X2APIC After Reset
,,10-42
X2APIC Transitions from x2APIC mode
,,1
10-42
2APIC Transitions from disabled mode
10-43
State Changes From XAPIC Mode to X2APIC Mode
10-43
10.12.6 Routing of Device Interrupts in X2APIC Mode
,10-43
10.12./ Initialization by System Software
,,,,10-43
10.12.8 CPUID EXtensions And Topology Enumeration
10-43
10.128.1
Consistency of APIC IDs and CPUID
10-44
10.12.9 CR Operation in x2APIC Mode
10-44
10.12.10 Determining lPl Destination in X2APIC Mode
10-45
10.12.10.1 Logical Destination Mode in x2APIC Mode
着1
10.12.10.2 Deriving Logical x2APIC id from the local X2APIC ID
10-46
10.12.11 SELF IPI Register..,......
10-47
10.13 APIC BUS MESSAGE FORMATS
,,,,,10-47
10.13.1 Bus Message Formats.
11
10-47
0.13. 2 EOI Message
1111
.10-47
10.132.1
Short messag
,10-48
10.13.2.2 Non-tocused Lowest Priority Message............
着看1
,10-49
10.13.2.3 APIC Bus Status Cycles
10-50
CHAPTER 11
MEMORY CACHE CONTROL
TERNAL CACHES TLBS AND BUFFERS
:::.
11.2 CACHING TERMINOLOGY
115
1,3 METHODS OF CACHING AVAILABLE
1着着11D鲁D141,1着111首1
11.3.1 Buf fering of Write Combining Memory locations
11.3.2 Choosing a Memory type...
11着看
11.3.3 Code Fetches in Uncacheable Memory
11-9
11.4 CACHE CONTROL PROTOCOL
着1着D1着
119
11.5 CACHE CONTROL
41
1能着11
11-10
x Vol. 3A
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