AD4111.pdfAD4111模数转换芯片datasheet，英文版，The AD4111 is

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详细说明：AD4111模数转换芯片datasheet，英文版，The AD4111 is a low power, low noise, 24-bit, sigma-delta (Σ-Δ) analog-to-digital converter (ADC) that integrates an analog front end (AFE) for fully differential or single-ended, high impedance (≥1 MΩ) bipolar, ±10 V voltage inputs, and 0 mA to 20 mA current inputs.Data sheet AD4111 REVISION HISTORY 8/2018-Revision 0: Initial version Rev.0 Page 3 of 59 AD4111 Data Sheet FUNCTIONAL BLOCK DIAGRAM AVDD REGCAPA REF- REF+ REFOUT lOVDD REGCAPD COMPBY OPEN WIRE BUFFERED DETECTION PRECISIO REFERENCE LDO VINO O VIN INT VIN3 O PRECISION VIN O RAIL TO RAIL VOLTAGE VIN5O REFERENCE DIVIDE VIN6 O INPUT BUFFERS VINZ O SCLK VINCOM O DIGITAL SERIAL DIN MUX VBIAS-O ∑AADc FILTER INTERFACE O DOUT/RDY lIN3+O l|N2+8 OSYN N1+ N0+ O ERROR 50Q N00 AD4111 IIN1-Q lIN2 |N3 XTAL AND INTERNAL iPASSIVES GPO CONTROL CLOCH。 SCILLATOR CIRCUITRY NTEGRATE囗 TEMPERATURE SENSOR AVSS GPOO XTAL1 XTAL2/CLKIO Figure 1 Rev.o Page 4 of 59 Data sheet AD4111 SPECIFICATIONS AVDD=3.0Vt055V IOVDD=2Vt0 55V, AvSS=0V, DGND=0V. VBIAS-=0V. REF+=2.5V,REF-= AVSS. internal master clock(mClk)=2 MHz, ta= TMIN to TMAx(40"C to +105C), unless otherwise noted Table 1 Parameter Test Conditions/Comments Min Typ Max Unit VOLTAGE INPUTS Differential Input Voltage Range Specified performance 10 Functio VREFX 10 +VoeUx 10 Absolute (Pin) Input voltage AVDD≥4.75V 20 +20 VvvV AVDD=3.0V 12 nput Impedance Offset error 25°C 1.5 Offset drift ±7 μV/C Gain error Internal full-scale calibration 25c 0.05 offs Gain Drift ±1 ppm/C Integral Nonlinearity(INL) 0.01 of FSr Total Unadjusted Error(TUE) 25°C, internal Vhb ±0.06 of fSr -40°Cto+105°C, internal VREF ±0.1 of FSr 25℃C, external v of fsr 40C to +105 C, external VreF ±0.08 of fSr Power Supply Rejection AVDD for VIn=1V dB Common-Mode rejection VIN=1V At do d B At 50 Hz, 60 Hz 20 Hz output data rate(postfilter),50 Hz+ 120 dB 1 Hz and60Hz±1Hz Normal mode rejection 4 50Hz±1 Hz and60Hz±1Hz Internal clock, 20 SPS ODR (postfilter) External clock, 20 SPS ODR(postfilter) Resolution See table 6 and table 8 ose See table 6 and Table 8 CURRENT INPUTS Input Current Range 0.5 Absolute(Pin Input Voltage AVSS-005 AVDD+0.055 V Input Impedance d 54 75 Offset error Offset Drift ±3 nA°C Gain error Factory calibrated gain, 25C ±0.02 offs Gain Drift ±10 ppm/C INL 0.01 of FSR TUE+ 25°C, internal BeeF of FSr -40%C to+105 C, internal VREF ±0.2 o of Fsr 25C, external VReF of FSR 40°Cto+105°C, external VReF ±0.2 of FSR Power Supply Rejection AVDD for In= 10 mA 0.5 Normal Mode rejection 50Hz±1 Hz and60Hz±1Hz Internal clock, 20 SPS ODR (postfilter) External clock, 20 SPS ODR(postfilter) 90 Resolution See table 7 and Table 9 Noise See table 7 and Table g ADC SPEED AND PERFORMANCE ADC Output Data Rate(ODR One channel. see table 6 1.25 31,250 SPS No Missing Codes EXcluding sinc3 filter 2 15 kHz notch 24 Bits Rev.0 Page 5 of 59 AD4111 Data Sheet Parameter Test Conditions/Comments Min Typ Max Unit INTERNAL REFERENCE 100 nF external capacitor to AVSS Output Voltage REFOUT with respect to Avss 2.5 Initial Accuracy REFOUT, TA= 25C -0.12 +0.12 o of v Temperature Coefficient ±5 +12 ppm/°Cc Reference Load Current, Iload 10 +10 mA Power Supply rejection AVDD (line regulation Load Regulation Vour/△ LoAD 32 ppm/mA Voltage Noise eN, 0.1 Hz to 10 Hz, 2.5 V reference 4.5 μvrms Voltage Noise Density eN 1 kHz. 2.5V reference 215 nV/√Hz Turn On Settling Time 100 nF REFOUT capacitor 200 Short-Circuit Current Isc 25 A EXTERNAL REFERENCE INPUTS Differential Input Range VREF=(REF+)-(REF- 2.5 AVDD Absolute Voltage Limits Buffers disabled AVSS-0. 05 AVDD+0.05 Buffers enabled AVSS AVDD REF± nput Current Buffers disabled Input Current HA/V Input Current Drift External clock ±0.75 nA/V/C Internal clock ±2 nA/V°C Buffers enabled Input Current ±100 nA Input Current Drift 0.25 nA°C Normal Mode rejection See the rejection parameter Common-Mode rejection 95 dB TEMPERATURE SENSOR Accuracy After user calibration at 25C °C Sensitivity 477 GENERAL-PURPOSE OUTPUTS With respect to AVSS (GPOO, GPO1) Floating State Output Capacitance Output Voltage+ High, VoH Source current(IsoURCE)=200 HA AVDD-1 LOW, Vol Sink current(IsINK)=800 HA AVSS+0.4 CLOCK Internal clock Frequency MHz Accuracy 2.5% +2.5% Duty Cycle 50 Output∨ oltage LOW, Vol 04 High, VOH 0. 8 x OVDD Crystal Frequency 14 16 16384 MHZ Start-Up Time 10 External Clock(CLKIO) 2 2.048 MHz Duty Cycle 30 50 70 % Rev.o Page 6 of 59 Data sheet AD4111 Parameter Test Conditions/Comments Min Typ Max Unit OGIC INPUTS Input voltage High,Ⅵ 2V< IOVDD<23V 0.65×|OVDD 2.3V≤|OVDD≤5.5V 0.7×|OVDD 2V≤|ovDD<2.3V 035× OVDDV 2.3V≤|OVDD≤5.5∨ 0.7 Hysteresis IOVDD≥2.7V 0.08 0.25 JOVDD<2.7V 0.04 0.2 Leakage current -10 +10 A LOGIC OUTPUT(DOUT/RDY Output volta High, VOH lOVDD24.5V ISouRCE= 1 mA 0.8×|OVDD 2.7V≤|OvDD<4.5 V, ISoURCE=500μA 0.8×|OVDD lOVDD< 2.7V, ISOURCE=200 HA 0.8×|OVDD LOW, Vol ovDD≥4.5 V, SiNK=2mA 0.4 2.7VS IOVDD<4.5V, SinK=1 mA 0.4 VvvV lOVDD<2.V, ISINK= 400 HA 0.4 eakage Current Floating state 0 A Output Capacitance Floating state 10 DF POWER REQUIREMENTS Power Supply Voltage AVDD to Avss 3.0 5.5 AVSs to dgnd 2.75 loVED to dgnd 5.5 Vvvv lOVEd to avss For avss< dgnd 6.35 POWER SUPPLY CURRENTS8 All outputs unloaded digital inputs connected to lovdd or dgnd Full Operating Mode AVDD Current Including internal reference 3.3 3.7 lOVDD Current Internal clock 0.6 08 Standby mode AlVIN=0V 120 AAAA Power-Down Mode AIL VIN=0V 90 POWER DISSIPATION Operating mode 19.5 Standby Mode 600 W Power-Down mode 450 W i The full specification is guaranteed for a differential input signal of +10V. the device is functional up to a differential input signal of +VREF X 10. However, the specified absolute(pin) voltage must not be exceeded for the proper functi 2 Following a system zero-scale calibration, the offset error is in the order of the noise for the programmed output data rate selected The gain calibration register is overwritten by performing an internal full-scale calibration Alternatively a system full-scale calibration reduces the gain error to the order of the noise for the programmed output data rate for the channel that is calibrated 4 Specification is not production tested but is supported by characterization data at the initial product release This maximum specification is only possible if INx- is biased so that the current through the resistor is less than 24 mA. It is not possible with lNx- connected to o v. 6 This specification shows the impedance seen between current input pins. The current is measured across a 50 Q sense resistor This specification includes moisture sensitivity level (Msl) preconditioning effects This specification is with no load on the refout pin and the digital output pins. Rev.0 Page 7 of 59 AD4111 Data Sheet TIMING CHARACTERISTICS IOVDD=2 V to 5.5 V, DGND =0 V, Input Logic 0=0 V, Input Logic 1=IOVDD, capacitive load( cload)=20 pF, unless otherwise noted Table 2 Parameter Li it Imit at I MIN MAx Unit Description, 2 SCLK ns min SCLK high pulse width 25 ns min SCLK low pulse width READ OPERATION ns min Stalling edge to dOUT/RDY active time ns max lOVDD=4.75V to 5.5 V ns max lOVDD=2Vto36v ns min SCLK active edge to data valid delay 12.5 ns max lOVDD=4.75V to 5.5 V ns max JOVDD=2Vto36v 2.5 ns min Bus relinquish time after Cs inactive edge ns max 0 ns min SCLK inactive edge to CS inactive edge 10 ns min SCLK inactive edge to doUt/RDY high/low WRITE OPERATION ns min CS falling edge to sCLK active edge setup time" 10 0885 ns min Data valid to SCLK edge setup time ns min Data valid to SCLK edge hold time t11 ns min CS rising edge to sClK edge hold time Sample tested during initial release to ensure compliance. 2 See Figure 2 and Figure 3 This parameter is defined as the time required for the output to cross the vo or voH limits The SCLK active edge Is the falling edge of SCLK 6 DOUT/RDY returns high after a read of the data register In single-conversion mode and continuous conversion mode, the same data can be read again if required, while DOUT/RDY is high. However, care must be taken to ensure that subsequent reads do not occur close to the next output update If the continuous read feature is enabled the digital word can be read only once Rev.o Page 8 of 59 Data sheet AD4111 Timing Diagrams ( ts DOUT/RDY (O) MSB t2 CLK ( I= INPUT.O= OUTPUT Figure 2. Read Cycle Timing Diagram SCLK O) DIN O ISB LSB = INPUT,0=。 UTPUT Fi 3. Write Cycle Ti Diagram Rev.0 Page 9 of 59 AD4111 Data Sheet ABSOLUTE MAXIMUM RATINGS TA= 25C, unless otherwise noted THERMAL RESISTANCE Table 3 Thermal performance is directly linked to printed circuit board Parameter Rating (PCB) design and operating environment. Careful attention to AyDD to Avss 0.3Vto+6.5V PCB thermal design is required A∨ DD to dgnd -0.3Vto+65V OJA is specified for a device soldered on a JEDEC test board for loVED to dgnD 0.3vto+65V surface-mount packages lOVDD to Avss 0.3Vto+7.5V AySS to dgnD 3.25Vto+0.3V Table 4. Thermal resistance V|Nⅹ to avss -50Vto+50V Package Type Unit lINX+ to Avss 0.3V to avdd+0.3V CP40-151 lINX- to Avss -0.3V to AVdd+0.3v 4-Layer JEDEC Board 34 °C/ Current Input Current .50 ma to +50 mA Thermal impedance simulated values are based on JEDEC 2S2P thermal test Reference Input Voltage to AVSS 03V to AVdd+0.3V board with 16 thermal vias. See JEDEC JESD51 Digital input voltage to dgnd 0.3V to ovId+0.3V Digital Output Voltage to DGND 0.3V to oDd+0.3v ESD CAUTION Digital Input Current 10 mA ESD (electrostatic discharge) sensitive device. Operating Temperature Range 40°Cto+105°C Charged devices and circuit boards can discharge without detection. Although this product features Storage Temperature Range -65°Cto+150°C patented or proprietary protection circuitry, damage Maximum Junction Temperature 150°C may occur on devices subjected to high energy ESd Lead Soldering, Reflow Temperature 260C Therefore, proper ESD precautions should be taken to avoid performance degradation or loss of functionality The absolute maximum current input current, current input voltage, and lINx-voltage must all be within the specified limits Stresses at or above those listed under absolute maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied Operation beyond the maximum operating conditions for extended periods may ffect product reliability Rev.0 Page 10 of 59

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