ADI Reference Design使用方法ADI Reference Design Proje

文件名称: ADI Reference Design使用方法

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详细说明：ADI Reference Design Project 的使用方法，以DAQ2為範例2019/4/18 Building HDL (Analog Devices Wiki An Altera project build is relatively easy. There is no need to build any library components. However, the flow is the sane,run maketo build your project of interest. In this example, I am only interested in the 'aDRv9371X project on the AlOSOC projects/adrv9371x/al0soc make Screen sho This assumes that you have the tools and licenses setup correctly. If you dont get to the last line, the make failed to build the project. There is nothing you can gather from the 'make output other than the build failed or not), the actual failure is in a log file. So let's see how to analyze the build log files and results If you want to usc a Nios-II based project with no-QS software, you have to turn off the Mmu feature of the Nios_II processor. In that case, the make will get an additional attribute make nios2 MMU=0 Altera: checking build and analyzing results If you look closely at the. rule tor this target, you see it is just calling quartus_sh with the project tCl tile and redirecting the output to a log file. In this case 'adrv9371-a10soc_quartus. log and is inside the projects/adrv9371x/a10soc' director ke: Entering directory /home/RKutty/gitadi/hdl/projects/adrv9371x/a10soc m -rf * log * INFO. txt k dump. txt db .asm. rpt *. done *eda. rpt *. fit. *. map k x sta. **qsf f sof * cdf * sld k gdf hc output system bd hps isw handoff hps sdr sy *ddr3 x, csv increme ntal db reconfig mif x. sopcinfo x. jdi x. pin x summary. csv * dpf quartus sh --64bit -t system _project. tcl > adrv9371xal0soc quartus log 2>&1 make: Leaving directory/ home/RKutty/gitadi/hdl/projects/ adrv9371x/a10soc Quick (or detailed)check on files. If you are seeking support from us, this is the most relevant in formation you can provide (do NOT copy paste make command line text) Is -ltr projects/adrv9371x/al0soc tail projects/adrv9371x/a10soC/adrv9371x a10soc quartuslog Screen shots: Screen shots And finally, if thc projcct build is succcssful, thc sopcinfo and sof files should bc in thc samc folder ls -ltr projects/adrv9371x/a10soc/*. sopcinfo ls -ltr projects/adrv9371x/a10soc* sof Screen shots You may now use this'sopcinfo' file as the input to your no-OS and or linux build. 'The sof file is used to program the devi Xilinx: build your desired project A Xilinx project is built the same way as an Altera' project. The only exception is that there are a few'sub-make(s) for the library components. In this example, I am building the DAQ2 project on the ' Zc706' carrer cd projects/dag2/2C706 make en shots https://wiki.analogcom/resources/fpga/docs/build 3/14 2019/4/18 Building HDL [Analog Devices Wiki 匚 bash /gitai/hd 1]>ma cts/daq/zc70 make: Entering directory /home/RKutty/gitadi /hdl/projects/daq2/zc706 TakE /li brary/axi_ad9144 make[1]: Entering directory ' /home/RKuttygitadi/hd1/library/axi_ad9144 / vivado -pde batch -source axi ad9144 ip, tcl >5 axi-ad9144-1p, log 24p 'es srcs * hw * sim data og component. xml . J 1i°,ip_ user fi1 make [1]: Leaving di rectory ' /home/RKutty/gitadi/hdl/library/axi-ad9144 make -C /library/axi_ad9680 make [1]: Entering directory ' /home/RKutty/gitadi/hdl/library/axi-ad968o Fri he * date 1 og component,xm°, Jou xou1°,ip_user_f1es喻,srcs,hw育,sim vivado -mode batch -source axi_ad9680-ip tcl > axi-ad9680_ip log 2>&1 make[1]: Leaving di rectory ' /home/RKutty/gitadihdl/library/axi-ad9680 make -./../ ../li brary/xilinx/axi_adcfifo make[1]: Entering directory ' /home/RKutty/gitadihdl/library/xilinx/axi_adcfifo rm -rf + cache * data *xpr * log component. xml * jou xgui *.ip_user_files *.srcs *hw*.sim vivado -mmde batch -source axi_adcfifo_ip, tcl > axi_adcfifo_ip log 2>&1 make [1]: Leaving di rectory /home/RKutty/gitadi/ hdl/library/xilinx/axi_adcf ifo make -C./././library/xilinx/axi-adxcvr make [1]: Entering directory '/home/RKutty/gitadi/hd1/library/xilinx/axi-adxcvr rm -rf *. cache * data *xpr * log component. xml * jou xgui *ip_user_files *srcs *hw.sim vivado -mode batch -source axi-adxcvr-ip, tcl > axi-adxcvr-ip, log 2>81 make [1]: Leaving directory/home/RKutty/gitadi/hdl/library/xilinx/axi-adxcvr make -./ ../../li brary/axi-clkgen make[1]: Entering directory '/home/RKutty/gitai/hdl/library/axi_clkgen rm-rf w cache *. data *xpr wlog component. xml * . jou xgui *ip_user_files * . srcs .hw *. sim vivado -mode batch -source axi-ckgen_ip, tcl > axi-clkgen_ip, log 2>81 [1]: Leaving di rectory /home/RKutty/gitadi/hdl/library/axi_clkgen make -C / brary/a×i_dmac make[1]: Entering directory '/home/RKutty/gitadi/hd1/library/axi_dmac make-C./util_axis_fifo/ reen shots 匚 bash make[1]: Leaving di rectory/home/'RKutty/gitadi/hdl/library/axi_hdmi_tx make -C./../../1i brary/axi_spdif_tx make [1]: Entering director ome/RKutty/gitadi/hdl/library/axi__tx °, cache°,data“,xpr,1 og component,xm“, Jou xgu°,ip_user-千1e5°,src5“,hw,sm vivado -mode batch -source axi_spdif tx_ ip tcl > axi_ spdif tx_ ip log 2>&1 lake [1]: Leaving di rectory/home/'RKutty/gitadi/hdl/library/axi_spdif make -∴,/../.1 ibrary/× linx/ util adxcvr make[1]: Entering directory ' /home/RKuttygitadi/hd1/library/xilinx/util-adxcvr cache°.data",xpr,1 og component,xm“,j0uxqu“, ip_user_t11es,srcs", .5m vado -mode batch -source util-adxcvr-ip tcl bs util-adxevr_ip log 25&1 make [1]: Leaving di rectory ' /home/RKuttygitadi/hdl/library/xilinx/util-adxcvr make-C./././i brary/util__cpack make [1]: Entering directory ' /home/RKuttygitadi/hdl/library/util_cpack vivado -mde batch -source util__cpack_ip tcl > util_cpack__1p. log 2>S * srcs *hwed *. sim rm -rf *.cache *data *xpr *. log component, xml *.jou xgui .ip_user_files *srcs*hw*.sim make [1]: Leaving directory ' /home/RKutty/gitadihdl/library/util_cpack make -C../../../li brary/util-dacfifo make [1]: Entering directory '/home/RKutty/gitadi/hd1/library /util-dacfifo m-rf“, cache“,dta“,xpr",1 og component,×m°, Jou gut“,ip_ user fi1es",srcs“,hw°,sim ri vado -mode batch -source util-dacfifo-ip tcl > util-dacfifo_ip log 2>81 make [1]: Leaving di rectory /home/RKutty/gitadihdl/library/util-dacfifo make-C /li brary/util_upack make [1]: Entering directory '/home/RKutty/gitadi/hdl/library /util_upack rm-rf“, cache°,dat 1 og component,xm°, jou xu1°,ip_ user fi1es,srcs,hw育,sTm vivado -mode batch -source util_upack_ip,tc make[1]: Leaving directory '/home/RKutty/gitadi/hdl/library/util_upack lvivado -mode batch -source system_project. tcl >> dag2_zc706-vivado log 287.Xi1 rm-rf. cache.data".xpr曾.1og".uxgu1.runs曾.srcs".sdk,h°.sim 十1 make: Leaving directory '/home/RKutty/gitadi/hdl/projects/daq2/zc706 [-/gitai/hd1]> https://wiki.analogcom/resources/fpga/docs/build 4/14 2019/4/18 Building HDL (Analog Devices Wiki The Imake builds all the libraries first and then builds the project. This assumes that you have the tools and licenses setup correctly. If you don t get to the last line, the make failed to build one or more targets it could be a library component or the project itself. There is nothing you can gather from the 'make output(other than which one failed), the actual failure is in a log file. So let's see how to analvze the build log files and results Xilinx: checking build and analyzing results of library components If you look closely, you see what it is actually doing It enters a library component folder then calls Vivado' in batch mode. The IP commands are in the source Tel file and output is redirected to a log file. In the below exanple that is axi_ad9144_iplog inside the 'library/axi ad9144' directory make[1]: Entering directory /home/RKutty/gitai/hdl/library/axi_ ad9144 rm -rf *. cache * data .xpr + log component. xml * jou xgui *ip user files * . srcs *.hw *.sim.X il vivado -mode batch -source axi ad9144 ip tcl > axi ad9144 ip, log 2>&1 If you see make returns an error (and stops), you must first check the contents of this log file before going crazy on us. You may also do a sanity checking just to see what are the generated files and the log file contents ls -ltr library/axi ad9 144 tail library/axi ad9144/axi ad9144 ip log Screen shots 匚 bash L-fgitadi/hd1]> Is -ltr library/axi_ad9144 1 RKutty Domain Users 2175 Feb 24 10: 44 axi_ad9144-constr xdc -rin-r--r--1 RKutty Domain Users 1671 Feb 24 10: 45 Makefile rw-r--r-- 1 RKutty Domain Users 10571 Feb 24 10:45 axi ad9144v -rw-r--r 1 RKutty Domain Users 16162 Feb 24 10:45 axi_ad9144_channelV rw-r--r-- 1 RKutty Domain Users 9533 Feb 24 10: 45 axi-ad9144_core.v rwxr-xr-x 1 RKutty Domain Users 6287 Feb 24 10: 45 axi__hw. tcl -rwnereer 1 RKutty Domain Users 6799 Feb 24 10: 45 ax1ad9144-1fv 1 RKutty Domain Users 1215 Feb 24 10: 45 axi_ad9144-ip tcl drinkr-xr-x+ 1 RKutty Domain Users 0Feb2410:51a1ad9144.h drwxr-xr-x+ 1 RKutty Domain Users o Feb 24 10: 51 axi_ad9144, cache r_files o Feb 24 10: 51 axi-ad9144ip_user _files drwr-×r-×+1 RKutty Domain Users drwxr-xr-x+ 1 RKutty Domain Users o Feb 24 10: 51 xqui -rwoxr-xr-x 1 RKutty Domain Users 11753 Feb 2410: 51 axi-ad9144xpr rwnkr-xr-x 1 RKutty Domain Users 48657 Feb 24 10: 51 component. xml rwoxr-xr-x 1 RKutty Domain Users 22111 Feb 24 10: 51 vivado log H-rwxr-xr-x 1 RKutty Domain Users 640 Feb2410:51v -rwI-r--t 1 RKutty Domain Users 22074 Feb 24 10: 51 axi_ad9144_iplog [-/gitai/hd1]> Screen shots https://wiki.analogcom/resources/fpga/docs/build 5/14 2019/4/18 Building HDL [Analog Devices Wiki 匚 bash /gitadi/hd1]> tail library/axi-ad9144/axi_ad9144-ip log INFO:[IP_Flow 19-4753J Inferred signal 'reset from port 's_axi_aresetn' as interface 's_as INFO:[IP-Flow 19-4728] Bus Interface'5_axi-aresetn': Added interface par ameter ' wi e 'ACTIVE_LOW INFO:[IP-Flow19-4728] Bus Interface '5_axi_aclk: Added interface parameter ' ASSOCIATED_RESE values axi aresetn t adi_ip_constraints axi_ad9144 [list #sad_hd_dir/li brary/common/ad_axi_ip_constr. xdc"] set_property driver_value o [i px: get_ports *dowf* -of_objects [ipx:: current_core set-property driver-value o [i px:: get_ports*dunf* -of_objects [ipx:: current_core A set-property driver-value o [i px: get-_ports tx_ready* -of _objects [i px: current_] i px: save_core [i px::current_core INFQ:[Comn 17-206] Exiting vivado at Fri Feb 24 15: 51: 10 2017 [/gitai/hd1]> Xilinx: checking build and analyzing results of projects The last thing make does in this above example is building the project. It is exactly the same rule as the library component. The log file, in this example, is called'daq2-_zc706_vivado log and is inside the 'projects/day2/zc706' directory rm -rf k, cache * data k. xpr * log * jou xgui k runs k. srcs *. sdk * hw *. sim xil *. ip user file vivado -mode batch -source system _ project. tcl >>dag2 zc706 vivado log 2>&1 make: Leaving directory /home/RKutty/gitadihdl/projects/dag2/zc706 Quick(or detailed) check on files Is -Itr projects/dag2/Zc706 tail projects/dag2/zc706/dag2 zc706 vivado log Screen shots https://wiki.analogcom/resources/fpga/docs/build 2019/4/18 Building HDL [Analog Devices Wiki 匚ba /gitadi/hd1]> Is -ltr projects/daq 2/zc706 total 5646 -rw-r--r--1 RKutty Domain Users 3444 Feb 24 10: 45 Makefile -rw-r--r-- 1 RKutty Domain Users 956 Feb 24 10: 45 systembd tcl -rw-r--r-- 1 RKutty Domain Users 6357 Feb 24 10: 45 systemLconstr xdc 1 RKutty Domain Users 486 Feb 24 10: 45 systemproject tcl 1 RKutty Domain Users 11249 Feb 24 10:45 systemtopv drwxr-xr-x+ 1 RKutty Domain Users o Feb 24 10: 54 dag2_zc706 hw drwxr-xr-x+ 1 RKutty Domain Users o Feb 24 10: 54 dag2_ zc706, ip_user_files drwxr-xr-x+ 1 RKutty Domain Users o Feb 24 10: 54 dag2 zc706, cache rwxr-xr-x 1 RKutty Domain Users 645 Feb 24 10: 54 vivado, jou drwxr-xr-x+ 1 RKutty Domain Users o Feb 24 10: 54 dag2_zc706 srcs rwkr-xr-x 1 RKutty Domain Users 1412000 Feb 24 11: 18 timing_synth. log drwxr-xr-x+ 1 RKutty Domain Users o Feb 24 11: 18 dag 2_zc706,runs rwxr-xr-x 1 RKutty Domain Users 17863 Feb 24 11: 42 dag2_ zc706 xpr -rwoxr-xr-x 1 RKutty Domain Users 1350098 Feb 24 11: 44 timing_impl. log drutr-xr-x+ 1 RKutty Domain Users O Feb 24 11: 44 dag2_zc706 sdk -roxr-xr-x 1 RKutty Domain Users 1475730 Feb 24 11: 44 vivado log rin-r-- 1 RKutty Domain Users 1484869 Feb 24 11: 44 daq2_zc706-vivado log [/gitai/hd1]> Screen shots 匚b [-fgitadi/hd1]> tail projects/daq2/zc706/daq2-_zc706 0g RAM32M = RAM32M (RAMS32, RAMS32, RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMD320:459 inst RAM32X1D=> RAM32X1D(RAMD32, RAMD32): 2 instances RAM64M = RAM64M (RAMD64E, RAMD64E, RAMD64E, RAMD64E): 176 instances open_run: Time (s): cpu = 00: 00: 55; el apsed = 00: 00: 54. Memory (MB): peak -2641.406; gain INFO: [Timing 38-2] Deriving generated clocks INFO: [Timing 38-91] UpdateTimingParams Speed grade:-2, Del ay Type mi n_max INFO: [ Timming 38-191] Multithreading enabled for timing update using a maxi mum of 2 CpUs report_timing_summary Time (s): cpu 00: 00: 56: el apsed 00: 00: 33. Memory (MB): peak- 27 gan=135.609 INFO:[Common 17-206] Exiting vivado at Fri Feb 24 16: 44: 05 2017. [/gitai/hd1]> And finally, if the project build is successful, the hdf file should be in the'sdk' folder https://wiki.analogcom/resources/fpga/docs/build 7114 2019/4/18 Building HDL (Analog Devices Wiki Is -Itr projects/dag2/zc706/daq2Zc706sdk Screen shots 匚 bash L-ygitadi/hd1]> 1s -ltr projects/daq2/zc706/daq2_zc706 sdk/ 56 rwpr-xr-x 1 RKutty Domain Users 2102541 Feb 24 11: 42 system top hdf [-/gitai/hd1 You may now use this hdf file as the input to your no OS and/or Linux build Tools Tool versions and environment Tools ADI providcs rcfcrcncc designs for both Altcra and Xilinx. Plcasc notc that we havc no prcfcrcncc ovcr Altcra or Xilinx, if projects.This is NOI a comparison (gcncric of athcrwisc)-this is what you should cxpcct and undcrstand when using AD possible we try to port the designs on both platforms. However, there are a few things you should be aware of when building th HDL repository on these tools. A red text indicates that you must pay extra attention Notes Altera Xilinx Main tools Quartus EDK Tools OSys IP Integrator SDK TooL Eclipsc-NiOS, Eclipsc-DS5 Eclipse Building library Do nothing. Quartus only need the_hw. tcl and Need to build each and every library component QSys parses them whenever invoked Vivado has its own way of identifying library components. This means you must build AlL the library components first before starting the project You must re-run these scripts if there are any modifications Building the project Source the system_project. tcl file Ti analysis The projects are usually tested and should be free of timing errors. There is no straightforward method to ify a timi CL proc by itself) on both the fail and return with an crror if the timing is not met (on both tools SDK(Microblaze/Nios) Use SOPCiNFo and Sof files Use hdf file SDK (ARM/FPGA combo) Not so well-thought procedure Need to run Same procedure as Mictolilaze different tools, manually edit build files etc. The stcps involved arc running bsp-cditor, running make, modlifying linker scripTs, makefiles and tO SDK https://wiki.analogcom/resources/fpga/docs/build 8/14 2019/4/18 Building HDL (Analog Devices Wiki Notes Altera Xilinx Upgrading/Version changes Quartus automatically updates the cores. Almost Vivado does not automatically update the revisions in (non-AD.I cores hassle-free for most of the cores. TCL flow (it does on GUD. It will stop at the first version mismatch(a rather slow and frustrating Tool versions Though thc DI libraries work across diffcrcnt versions of the tools, thc projects wc providc may not. Thc Xilinx and Altcra IPs may or may not work across versions. We can only assure you that they are tested and works only for the versions we provide I he projects are usually upgraded to the latest tools after they are publicly released. 'The information about the version of the. usedtoolscanbefoundinthereadMemd[https://github.com/analogdevicesinc/hdl/blob/master/readme.mdfileofeach branch. The script, which builds the project always double check the used tool version, and notifies the user, if he or she trying to use an unsupported version of tools There are several ways to find out which tool version you should use. The easiest way is to check the release notes Thttps://githnb.com/analogdevicesinc/hdl/releases].Youmayalsocheckoutorbrowsethedesiredbranchandveritythetool version in the base Tcl script(/hdl/projects/scripts /adi_project. tcl Chttps://github.com/analogdevicesinc/hdl/blobimaster/projects/scripts/adi_nrojecttc#l10),whichbuildstheprojects Environment As said above, our recommnended build flow is to use make and the command line versions of the tools. This method highly facilitates our ovcrall build and rclcasc proccss as it automatically builds thc rcquircd libraries and dcpcndcncics Linux environment setup All major distributions should havc 'makc installed by default. If not if you try the command it should tcl you how to install them with the package name. You may have to install git(sudo apt-get install git)and the Altera and Xilinx tools. These tools ome with certain settings*.sh scripts that you may source in your bashrc file to set up the environment. You may also do this manually(for better or worse), the following snippet is from a. bashrc file. Please note that unless you are an expert at manipulating these things, leave it to the tools to set up the environment export PATH=PATH: /opt/xilinx/Vivado/2016. 2/bin export PATH=S PATH: /opt/altera/16.0/quartus/ bin Windows environment setup ThebestoptiononWindowsistouseCygwin[https://www.cygwin.com].WHeninstallingitselectthemakeandgit'packages The manual changes to your. bashrc' do a lot look like that of thc linux environment export PATH=$ PATH: /cygdrive/d/Xilinx/Vivado/2015.4/ bin export PATH= PATH: /cygdrive/d/altera/15.1/ quartus/bin64 If you do not want to install Cygwin, there may still be some alternatives. There are make alternatives for windows command prompt, minimalist gI. for Windows ( Mingw), or the 'cygwin variations installed by the tools itself. Some of these may not be fully functional with our scripts and or projects. If you are an Altera user, the"Nios ll Command Shell "do support make. If you are a Xilinx user, use the gnuwin installed as part of the SDK, usually C: Xilinx\SDK\2015. 4 \gnuwin\ bin https://wiki.analogcom/resources/fpga/docs/build 9/14 2019/4/18 Building HDL (Analog Devices Wiki Make: supported targets Make[https://www.gnu.org/softwarc/makc/manual/makc.htmlisabuildautomationtoolwhichusesMakefile(s)to define a set of directives (rules) about how to compile and or link a program Targets,) In general, always run'make within a project folder such as 'hdll/projects/fmcomms2/a10gx'or "hdl/projects/fmcomms2/zc706'. There should not be a need for you to run'make'inside the library or root folders.The'make framework passes the top level targets'to any sub-makes inside its sub-folders. What this means is that if you run make inside hdl/ projects/fmcomms2, it builds all the carriers Cac701, 'a10gx'to'zcu102) which is an overkill The following targcts' arc supported argument description This builds everything in the current folder and its sub-folders, see context examples below make C library/axi_ad9122 all; Ti build AD9122 library component (Xilinx only) make: libraty all;## build ALL library components insidle'lilorary(Xilinx only) makc-C projects/fmcomms2/ zc706 all;## build FMCOMMS2-_ZC706(Xilinx)projcct make-C projects/fmcomms2/a10gx all;## build FMCOMMS2_ A10GX (Altera) project make-C projects /fmcomms2 all; ###f build FMCOMMS2 ALL carrier (including Altcra Xilinx) projects make-C projects all; ##f build aLL projects(something you really should not doy cle This removes all tool and temporary files in the current folder and its sub-folders, same context as above clcan-all This removes morc things() samc contcxt as abovc lib This is same as all in the library folder, ignored inside project folders. projectplatform This is a special target available only in the '! root folder and is ignored everywhere else, see syntax belo make fmcomms2. a10gx; #t build projects/fmcomms2/ a10gx make fmcomms2. zc706; #f build projects/fmcomms2/ zc706 Xilinx auto tcl build We do not recommend using this flow(crcatcd mostly for Windows uscrs that can t uSc gN. makc). Thc bencfit of this flow is that a user can build all desired libraries without manually building each library. The disadvantage comparing with makc is that the script will rebuild an Ip rcgardlcss if its sources wcrc modified or not(timestamp comparison Open Vivado. GUI, and the Tcl console type cd c: /github/ hdl/projects/dag2/ zc706 source ././scripts/adi make tcl This will get you access to https://wiki.analogcom/resources/fpga/docs/build 10/14

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