Remote Update IP远程更新Intel®FPGA IP核心使用支持设备中可用的专用远程系

文件名称: Remote Update IP

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详细说明：远程更新Intel®FPGA IP核心使用支持设备中可用的专用远程系统升级电路实现设备重新配置。远程系统升级可以帮助您在不召回产品的情况下交付特性增强和bug修复，减少上市时间，并延长产品寿命。远程更新英特尔FPGA IP核心命令配置电路开始重新配置周期。UG-31005|2018.11.26 intel Send Feedback 1. Remote Update Intel FPGA IP User Guide The Remote Update Intel FPGA IP core implements a device reconfiguration using dedicated remote system upgrade circuitry available in supported devices. Remote system upgrade helps you deliver feature enhancements and bug fixes without recalling your product, reduces time-to-market, and extends product life. The Remote Update Intel FPGA IP core commands the configuration circuitry to start a reconfiguration cycle The dedicated circuitry performs error detection during and after the configuration process. When the dedicated circuitry detects errors, the circuitry facilitates system recovery by reverting back to a safe, default factory configuration image and then provides error status information The following figures shows a functional diagram for a typical remote system upgrade pre ocess Figure 1. Typical Remote System upgrade process ontrpl module receive data from network Flash Remote System and update the new image into Controller New Application Image Configuraton Data Upgrade sue he flash Development Location sent through network Module 〔 ontro| Module trigger reconfiguration tc new image using RSU IP core RSU IP CCI Intel recommends that you use the following remote Update Intel fPGa ip core input clock (fmax) values 10 MHz- for arria B ii and stratix iv devices 20 MHZ-for other supported devices Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.s. and or other countries. Intel warrants performance of its FPGa and semiconductor products to current specifications in ISO accordance with Intel's standard warranty but reserves the right to make changes to any products and services 9001:2015 at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any Registered information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. *other names and brands may be claimed as the property of others intel 1.Remote Update Inte/ FPGA IP User Guide UG-31005|2018.11.26 Figure 2. High-Level Block Diagram of Remote System Upgrade Passive serial and Fast passive parallel Active serial Active parallel Confiquration Scheme Configuration Scheme Configuration Scheme FPGA FPGA FPGA (Cyclone /v devices only) Nios l Processor NioS‖ Processor Nios‖ Processor or User logic or User Logic or User logic EPCS Supported Flash EPCQ or Paralllel Memory EPCQ-L Flash MAXII MAXV or MAX 10 Note The remote system upgrade feature support for each configuration scheme varies between device family. For more information about the configuration scheme and the remote system upgrade feature please refer to the configuration chapter of the respective device family handbook. Related Information Remote Update Intel FPGA IP Core Knowledge Base Configuration Support Center Introduction to intel fPga ip cores Provides general information about all intel FPga iP cores, including parameterizing generating upgrading and simulating Ip cores Creating Version-Independent Ip and Qsys simulation Scripts Create simulation scripts that do not require manual updates for software or IP version upgrades Project Management best practices Guidelines for efficient management and portability of your project and Ip files Remote Update Intel FPGA IP User Guide Archives on page 38 Provides a list of user guides for previous versions of the remote Update Intel FPGA IP core 1.1. Avalon -MM in Remote Update Intel FPGA IP Core The avalon -MM interface is supported in the remote update intel FPGa IP core. You can only use the IP core either with or without Avalon-MM interface. You can instantiate the Avalon -MM Interface by turning on the Add support for Avalon Interface option in Remote Update Intel FPGA IP parameter editor. Note The Avalon -MM support for Remote Update Intel FPGA IP core is available in Intel Quartus Prime software version 15.0 and onwards. Remote Update Intel FPGA IP User Guide Send Feedback 4 1. Remote Update Inte/ FPGA IP User Guide intel? UG-31005|201811.26 Figure 3. Remote Update Intel FPGA IP Core Implementation with and without Avalon- MM Interface Figure shows the Avalon Remote update support architecture which consists of 2 components Remote Intel FPGA IP core and avalon remote update controller. If Avalon interface is enabled the conduit interfaces of Remote Update Intel FPGA IP core will connect to conduit interface of the controller. Remote Update Intel FPGA IP Core Remote Update Intel FPGA /P core without Avalon-MM Interface Avalon remote Remote Update Update Controller Intel FPGA IP Core Remote Update intel FPGA /P core with Avalon-MM Interface 1.2, Intel Arria 10 Devices 1.2.1. Remote System Configuration Mode Remote configuration supports Direct to application"(DTA) andApplication to Application"update. Remote configuration only supports a 4-byte address scheme so there is no support for devices with densities smaller than 128 Mbit □ Send Feedback Remote Update Intel FPGA IP User Guid 5 intel 1.Remote Update Inte/ FPGA IP User Guide UG-31005|2018.11.26 Figure 4. Transitions Between Factory and Application Configurations in Remote pdate Mode Trigger reconfiguration Start Address =0 After por or Trigger reconfiguration start Address=0 or externaly pulse n CONFIG n CONFIG assertion or externaly pulse nCONFIG Read start address Error count <=3 from flash Factory configuration Application Configuration Load Factory POF Error Count>3 Load Application mber pol → Reconfiguration& Reconfiguration Start address >0 Start Address= 32 and not 32 Watchdog No Er ATimeout Enter Factory Enter Application User me User mode Reconfiguration Reconfiguration Start address >o and not 32 Start address= 32 When you use low-voltage quad-serial configuration(EPCQ-L) devices, the remote update mode allows a configuration space to start at any flash sector boundary. This capability allows a maximum of 512 pages in the EPCQ-L256 device and 1024 pages in the epco-L512 device, in which the minimum size of each page is 512 Kbits Additionally, the remote update mode features an optional user watchdog timer that can detect functional errors in an application configuration Note When error occurs, the as controller will load the same application configuration image for three times before reverting to factory configuration image by that time the total time taken exceeds 100ms and violates the pcle boot-up time when using CyP configuration mode. If your design is sensitive to the pcie boot-up requirement Intel recommends that you do not use the direct-to-application feature Note Intel recommends that you set a fixed start address and never update the start address during user mode. You should only overwrite an existing application configuration image when you have a new application image. This is to avoid the factory configuration image to be erased unintentionally every time you update the start address Remote Update Intel FPGA IP User Guide Send Feedback 6 1. Remote Update Inte/ FPGA IP User Guide intel UG-31005|201811.26 1.2.2. Remote System Configuration Components Table 1 Remote System Configuration Components in Intel Arria 10 Devices Components Details Page mode feature The dedicated 32-bit start address register holds the start address Factory configuration Factory configuration can be set as the default configuration setup depending on the address pointer set. The factory configuration loads into the device upon power-up If a system encounters an error while loading application configuration data or if the device reconfigures due to assertion, the device loads the factory configuration. The remote system configuration register determines the reason for factory configuration Based on this information, the factory configuration determines which application configuration to load Application Application configuration can be the default contiguration setup depending on the address pointer configuration The application configuration loads into the device upon power-up. The application configuration is the configuration data from a remote source and the data is stored in different locations or pages of the memory storage device, excluding the factory page Watchdog timer a watchdog timer is a circuit that determines the functio na lity of another mechanism. the watchdog timer functions like a time delay relay that remains in the reset state while an lication runs Intel Arria 10 devices are equipped with a built-in watchdog timer for remote system configuration to prevent a faulty application configuration from indefinitely stalling the device The timer is a 29-bit counter but nly the upper 12 bits to set the value for the watchdog The timer begins counting after the device goes into user mode. To ensure the application configuration is valid, you must continuously reset the watchdog within a specific duration during user mode operation If the application configuration does not reset the user watchdog timer before time expires the dedicated circuitry reconfigures the device with the factory configuration and resets the user watchdog til Remote update sub- The remote update sub-block manages the remote configuration feature. A remote configuration black state machine controls this sub-block. This sub-block generates the control signals required to control the various configuration registers Remote configuration The remote configuration registers keep track of page addresses and the cause of configuration registers errors. You can control both the update and shift registers. the status and control registers are controlled by internal logic, but are read via the shift register. the control register is 38-bits wide For details about configuration registers, refer to the Configuration Design Security and Remote System Upgrades chapter in the Inte/ Arria 10 Core Fabric and General Purpose I/Os Handbook Related information Intel Arria 10 Core Fabric and general Purpose i/os Handbook Provides more information about configuration registers of the Intel arria 10 devices 1.2.3. Parameter Settings Table 2 Remote Update Intel FPGA IP Core Parameters for Intel Arria 10 Devices GUI Name Values Description REMOTE Specifies the configuration mode of the remote Update Intel FPGa ip col EPCQ-L device Choose the configuration device you are using ontinued □ Send Feedback Remote Update Intel FPGA IP User Guid intel 1.Remote Update Inte/ FPGA IP User Guide UG-31005|2018.11.26 GUI Name Values Description Enable this if you need to write configuration parameters Enable this if you are using Avalon interface Not available as this option is handled by the FPGa as controller instead of the remote update intel FPGA Ip core. The same application image is loaded for three times before reverting to factory application image,to ensure no unexpected system failure occurred. 12.4. Ports Table 3 Remote Update Intel FPGA IP Core Ports for Intel Arria 10 Devices Name Port Required? Description Inout Read signal for the parameter specified in input port and output port Signal indicating the parameter specified on the should be read the number of bits set on depends on the parameter type the signal is sampled at the rising clock edge assert the signal for only one clock cycle to prevent the parameter being read again in a subsequent clock cycle. The busy al is activated as is read active. While the parameter is being read, the busy signal remains asserted and has invalid data. when the busy signal is deactivated and has a valid data, another parameter can be read Input Write signal for parameter specified in and with value n written into remote update block with the value specified in e Signal indicating parameter specified with should be The number of bits read fre depends on the parameter typ he signal is sampled at the clock edge. The signal should be asserted for only one clock cycle to prevent the parameter from being rewritten on a subsequent clock cycle. the busy signal is activated as soon as is read as being active. While s being written, the busy signal rem is ignored. When the busy signal d ted another parameter can be written. This signal is only valid in factory configuration mode because parameters cannot be written in Application configuration mode Input Bus that specifies which parameter need to be read or updated A 3-bit bus that selects the parameter to be read or updated. If left unconnected, the default value for this port is 000 Input Data input for writing parameter data into the remote update block. Input bus for parameter data For some parameters, not all bits are used. In this case the lower order bits are used (for example status values use bits If left unconnected this bus defaults to 0. The port is ignored if the is the applic A 32-bit bus width(4-bytes addressing configuration device, for example EPCQ-L256)in the intel Quartus Prime software version 14.0 or later. continued. Remote Update Intel FPGA IP User Guide Send Feedback 8 1. Remote Update Inte/ FPGA IP User Guide intel UG-31005|201811.26 Name Port Required? Description Input Yes Signal indicating that reconfiguration of the part should begin using the current parameter settings a value of 1 indicates reconfiguration should begin. This signal is ignored if the signal is asserted to ensure all parameters are completely written before reconfiguration begins Inpu Reset signal for watchdog timer. Signal indicating the internal watchdog timer should be reset. Unlike other inputs, this signal is not affected by the signal and can reset the timer even when the signal is asserted A falling edge of this signal triggers a reset of the user watchdog timer For the timing specification of this parameter, refer to the specific device handbook Input Clock in put to the remote update block Clock input to control the machine and to drive the remote update block during the update of parameters This port must be connected to a valid clock. Input This is an active high signal. asserting this signal high will reset the Asynchronous reset input to the ip core to initialize the machine to a alid state the machine must be reset before first use, otherwise the state is not guaranteed to be valid Output Busy signal that indicates when remote update block is reading or While this signal is asserted, the machine ignores most of its inputs and cannot be altered until the machine deasserts this signal Therefore, changes are made only when the machine is not busy This signal goes high when is asserted, and remains high until the read or write operation completes Output No Data output when reading parameters This bus holds read parameter data from the remote update block The value specifies the parameter to read. When the signal is asserted the parameter value is loaded and driven on this bus. Data is valid when the busy signal is deasserted If left cted, the default value for the port is o The width of this bus is device-dependent. For the Intel Quartus Prime software version 14.0 and later, the bus width is 32-bit-using 4-byte addressing configuration device, for example EPCQL-256 Input This port allows you to select which register to be read whenever operation is runnin A logic high selects the Control Register-register containing the current remote update settings such as watchdog timer settings configuration mode(anF), and page address. A logic low selects the Update Register-register containing nilar data as held in the control register but the values are updated via operation for use in next econfiguration □ Send Feedback Remote Update Intel FPGA IP User Guid 9 intel 1.Remote Update Inte/ FPGA IP User Guide UG-31005|2018.11.26 1.2.5。 Parameters Table 4 Parameter Type and Corresponding Parameter Bit Width Mapping for Intel Arria 1o Devices Bit Parameter Width Comments Bit 4 User watchdog timer timeou ·Bit3 External configuration reset it Configuration reset triggered 000 Reconfiguration trigger from lagic array 000 conditions(Read Only asserted by an external device as the result of an err Bit o CRC error during applic figuration he por value for all bits are o 001 Illegal value 010 Watchdog Timeout Value 12 011 Watchdog Enable 100 Page Select 32 For the Intel Quartus Prime software version 14.0 and later: Width of 32 whe ding and writing the start add For active serial devices using 32-bit addressing such as EPCQL-256 corresponds to the upper 30 bits of the 32-bits start address is read as 101 Configuration Mode(AnF This parameter is set to 1 in application page and is set to o in factory page. In remote update mode this parameter can be read and written Before loading the application page in remote update mode intel recommends that you set this parameter to 1. The content of the control register cannot be read properly if you fail to do so 110 Illegal value 111 Illegal value 1.2.6 Avalon-MM Interface 1.2.6.1. Control Status Register Signals Table 5 Remote Update Intel FPGA IP Core Avalon-MM Control Status Register Signals for Intel Arria 10 Devices Name Width Direction Description 1 Input Clock in put np Reset input Input Address bus Input Perform a read transaction Input Perform a write transaction 32 Output Read data from Ip continued Remote Update Intel FPGA IP User Guide Send Feedback 10

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