DE0-MY_first_niosii，包括硬件设计，软件设计。nios开发的整个流程学习teras

文件名称: DE0-MY_first_niosii

所属分类: 硬件开发

开发工具:

文件大小: 4mb

下载次数: 0

上传时间: 2019-03-04

提供者: ansi*****

下载 (4mb)

不能下载？报告错误

详细说明：DE0-MY_first_niosii，包括硬件设计，软件设计。nios开发的整个流程学习terasIc Chapter 1 Hardware Design This tutorial provides comprehensive information that will hclp you undcrstand how to crcatc a FPGa based SoPC system implementing on your FPGa development board and run software upon The Nios ii processor core is a soft-core central processing unit that you could program onto an Altcra ficld programmable gate array(FPGA). This tutorial illustrates you to the basic flow covering hardware creation and software building. You are assumed to have the latest Quartus II and NIOS II EDS software installed and quite familiar with the operation of windows Os. If you use a different Quartus II and NIOS II EDs version, there will have some small difference during the operation. You are also be assumed to possess a SoCKit development board (other kinds of dev Board based on Altcra FPGa chip also supported) The example NioS Ii standard hardware system provides the following necessary components Nios lI processor core, thats where the software will be executed On-chip memory to store and run thc software JTAG link for communication between the host computer and target hardware(typically using a USB-Blasterll cable LED peripheral I/O(PIO), be used as indicators This section describes the flow of how to create a hardware system including sopc feature 1. Launch Quartus II then select - start to create a new project. See Figure 1-1 and Figure 1-2 teras www.terasic.com terasIc Ⅱ File Edit View Prcject Assignments Processing Tools Window Hel 早x Close 意 Close Project A File Properti Up nvert Progran Print 早x Recent file III Recent projects n三上F4 Edi- Settin D□ Netlist viewers Assistant( Post-Mappi D≥ [/C Assicnren: Analysis Dp三 atly Timing e丈mahe 早Tpe 工D tarts the New Project Wizard teras www.terasic.com terasIc New Project \ wizard Directory, Name top-Level Entity page 1 of 5 t is the working director for this projEct? e130 what Is the nane of thls prolect hat is the nane of the top-level dssign etly for this project? This na is case ser sitive and mLst exactly match t e entity name in the design file Use Existing Pioject lettings I B[>□ FinishCarrel[Her 2. Choose a working directory for this project, type project name and top-level entity name as shown in Figure 1-3. Then click you will see a window as shown in Figure 1-4 teras www.terasic.com Ry Nein PrnjPrt wizard Directory Name top-Level Entity page 1 of 5 wwhat is the working director for this Project? st NiosII wwhat is thE ame of this project 卜yFs爪sI what is the ame of the top-level design entity for dis project? This name is case sensitive a d must exactly match the entity name r the design file My-First_nosII [[Firsh[[ Hek 3. Click to next window. We choose device family and device settings. You should choose settings the same as the Figure 1-5. Then click to next window as shown in Figure 1-6 teras www.terasic.com terasIc y Neur! Project Vu zard Family Device Settings [ page 3 of 5] Select the family and device yo i want to target for compilation If y] don't have your cevices installed you can add therr using Device [nstaller fron tools nenu Device family Show in available devices list FaT: Cyclone V(/G,5刈闷) Packer DeviCes: A In count r Target de t Auto device selected by the Fitter Name Filt o Specific de ice selected in Available deVices" list 回 Show adwanced devices□ HardCop compa:ible only O Other: nfa Lore Voltage ALMs User i/Os GXB Channel pMA GXB channel pcs Pcle (pIpe) Hard Il 5b∠比11W 419:0342 419:0 5CNFC6D6F31C7…1 419 5CFC6D6F31C8.1.1 19 5c3Fc606817-11 1904999 Cu lydI iuni deviL HEro Limit DSP RAM to Hardcopy device resources <≥ FiYshCancel Hele teras www.terasic.com terasIc Neurs Project Ww zard EDA Tool Settings [page 4 of 5] peaify the othe eda tools used with the quartus ii software to develop your project EDA tools ToN≡r Formats) rln Tool automatica Des gn Entry/ thesis Run this tool automatically to syrt esize the current des gn mOney L Run gate-level simulation automat cally after compilation formal verIFication None> Boad -Level Signal integr it ≤B>□「( ction temperate 0-器5C Back Next> Finish Can:el teras www.terasic.com

(系统自动生成,下载前可以参看下载内容)