MT29F16G08ABABA_nandflashmicron大容量nandflash存储芯片，MT

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详细说明：micron大容量nandflash存储芯片，MT29F16G08ABABA, MT29F32G08AFABA, MT29F64G08A[J/K/M]ABA, MT29F128G08AUABA, MT29F16G08ABCBB, MT29F32G08AECBB, MT29F64G08A[K/M]CBB, MT29F128G08AUCBBMicron Confidential and Proprietary Micron 16Gb, 32Gb, 64Gb, 128Gb Asynchronous/Synchronous NAND F eatu ures Contents Important Notes and warnings........................... General description 10 Asynchronous and Synchronous Signal Descriptions... Signal Assignments…… Package Dimensions… 16 Architecture 21 Device and array organization ····· 22 Bus Opcration- Asynchronous Interface.…… 30 Asynchronous Enable Asynchronous Bus idle 30 Asynchronous Pausing Data Input/ Output………,…,…,…,…,…,…,…,… 31 Asynchronous Commands 31 Asynchronous addresses 32 Asynchronous Data Input…………… 33 Asynchronous Data Output.......…..… 4·重垂垂 34 Write protect 35 Ready/ Busy# 35 Bus Operation- Synchronous Interface 40 Synchronous Enable/Standby........... 41 Synchronous Bus Idle/Driving 41 Synchronous Pausing Data Input/ Output…….….….… 42 Synchronous commands....................................142 Synchronous addresses 43 Synchronous DDR Data Input.……… ·· 44 Synchronous DDR Data Output…,,… 45 Write protect 音看音D垂面垂 D垂垂 ∴47 Ready/Busy#…,…,…,…,…,…,…,…,…,…,…,……,…,…,…,…,,……,,…47 Deviceinitialization.......44w...............4....44.w..4...........wwwww.....48 Activating Interfaces…… 50 Activating the Asynchronous Interface 50 Activating the Synchronous Interface……………… 看垂着 50 Command definitions …………………J2 Reset Operations ..54 RESET(FFh).................... 54 SYNCHRONOUS RESET (FCh)..... 55 Identification Operations 56 READ ID (90h)..... 56 READ ID Parameter Tables 57 Configuration Operations…… 58 SET FEATURES (EFh)...................................... 58 GET FEATURES (EEh)...... 59 READ PARAMETER PAGE (ECh) .·垂 63 Parameter Page Data Structure Tables 64 READ UNIQUE ID(EDh),,…,,… Status operations ……,…"…72 74 READ STATUS (7Oh 75 READ STATUS ENHANCED(78h 76 Column Address Operations ,77 CHANGE READ COLUMN (05h-EOh) 77 CHANGE READ COLUMN ENHANCED(06h-EOh PDF:CCMC05-816717818-10495 Micron Technology, Inc. reserves the right to change products or specifications without notice. Rev. 1/18 EN e 2009 Micron Technology, Inc. All rights reserved Micron Confidential and Proprietary Micron 16Gb, 32Gb, 64Gb, 128Gb Asynchronous/Synchronous NAND Features CHANGE WRITE COLUMN (85h) CHANGE ROW ADDRESS (85h) 80 Read operations…,…,…… 82 READ MODE (OOh) 84 READ PAGE(OOh-30h).................. 85 READ PAGE CACHE SEQUENTIAL (31h 86 READ PAGE CACHE RANDOM (00h-31h) 87 READ PAGE CACHE LAST (3Fh) 89 READ PAGE MULTI-PLANE (00h-32h Program Operations.... 92 PROGRAM PAGE (80h-10h) 92 PROGRAM PAGE CACHE (80h-15h)...........................................94 PROGRAM PAGE MULTI-PLANE ( Erase Operations……,…,,, ∴98 ERASE BLOCK (60h-DOh) ·· 98 ERASE BLOCK MULTI-PLANE (60h-Dlh) 99 Copyback Operations 100 COPYBACK READ(00h-35h)………....,101 COPYBACK PROGRAM(85h-l0h)∴….11.1111 ·...·..:· 102 COPYBACK READ MULTI-PLANE (00h-32h) 102 COPYBACK PROGRAM MULTI-PLANE (85h-1lh) 103 One-Time Programmable(OTP)Operations 4 看垂着 104 PROGRAM OTP PAGE (80h-10h) 105 PROTECT OTP AREA(80h-10h 看垂4垂音··4音音垂 106 READ OTP PAGE (00h-30h) 107 Multi-Plane operations 108 Multi-Plane addressing .... l08 Intcrlcavcd Dic (Multi-LUN) Opcrations 108 Error Management,…,…,…,……,…,…,…,…,…,…,…,…,…,…,…,………,…,…,…,…,110 Output Drive Impedance Lll AC Overshoot/ Undershoot Specifications…….…….……..….….….….….….,….,...….….….114 Synchronous input slew Rate 量看 115 Output Slew rate 116 Electrical Specifications……,…,…,…,…,…,……,… ···:·::·.· 117 Electrical Specifications- DC Characteristics and Operating Conditions( Asynchronous)……,…,…,…,119 Electrical Specifications-DC Characteristics and Operating Conditions(Synchronous 120 Electrical Specifications- DC Characteristics and Operating Conditions(vccQ)…………………120 Elcctrical Specifications- AC Characteristics and Operating Conditions( Asynchronous)………………,123 Electrical Specifications-AC Characteristics and Operating Conditions(Synchronous) 125 Electrical Specifications- Array Characteristics 128 Asynchronous Interface Timing Diagrams………………… 129 Synchronous Interface Timing Diagrams ............. 140 Revision histor 162 Rev. f Production -1/18 162 Rev.E, Production-3/10……,162 Rev. D. Production -1/10 ..162 Rev.C-9/09 l62 Rcv.B-2/09 l62 Rev.A-1/09 番着4音音垂 D看音垂D l63 PDF:CCMC05-816717818-10495 Rev. 1/18 EN 4 Micron Technology, Inc. reserves the right to change products or specifications without notice. e 2009 Micron Technology, Inc. All rights reserved Micron Confidential and Proprietary Micron 16Gb, 32Gb, 64Gb, 128Gb Asynchronous/Synchronous NAND F eatu ures List of tables Table 1: Asynchronous and Synchronous Signal Definitions…,…,…,, 10 Table2: Array Addressing for Logical Unit(LUN)……,…,…,…,…,…,…,…,…,…,……,,……………29 Table 3: Asynchronous Interface Mode selection 30 Table 4: Synchronous Interface Mode Selection 40 Table 5: Command set 52 Table 6 Read id Parameters for Address ooh ∴57 Table 7: Read id parameters for address 2oh 57 Table 8: Fcature Address dcfinitions 垂4音 58 Table 9: Feature Address Olh: Timing Mode. .........................60 Table 10: Feature Addresses 10h and 80h: Programmable Output Drive Strength 60 Table1l: Feature Addresses8lh: Programmable r/B# Pull-Down Strength…………… 61 Table 12; Feature Addresses90h: Array Operation Mode∴…,,…,…,…,…,…,…,,…,6l Table 13: Parameter Page Data Structure 64 Table 14: Status Register Definition………… 74 Table 15: OTP Area details 105 Table 16: Error Management details l10 Table 17: Output Drive Strength Conditions(cQ=1.7-1.95V)………………………………………………llL Table 18: Output Drive Strength Impedance Values (VCco =1.7-1.95V) Table 19: Output Drive Strength Conditions(vcQ=2.7-3.6Ⅵ)…… 112 Table 20: Output Drive Strength Impedance Values (V 2.7-3.6V) l12 Table21: Pull-Up and Pull-Down Output Impedance Mismatch……,…,…,…,,… 113 Table22; Asynchronous Overshoot/ Undershoot parameters………,…,…,…,…,…,…,…,114 Table 23: Synchronous Overshoot/Undershoot Parameters 114 able24: Test Conditions for Input Slew Rate….…,…,…,……,…,… Table 25: Input Slew Rate(VccQ-1.7-1.95V) 115 Table 26: Test Conditions for Output Slew Rate 音音面面看垂垂番 D垂垂 n116 Table27: Output Slew Rate(Vcc=1.7-1.95V)…………………………………………116 Table28: Output Slew rate(vcco=2.7-3.6V)………116 Table29: Absolute maximum ratings by device.………17 Table 30: Recommended Operating Conditions l17 Table31:Ⅴ alid Blocks per Lun……………,…,…,…,…,…,…,…,…,…,…,…,…,…………,117 Table32; Capacitance:100- Ball BGA Package……,…,…,…,…,…,…,…,…,…,…,118 Table 33: Capacitance: 48-Pin TSOP Package Table34: Capacitance:52- Pad lga package……………… 垂看着看垂D 垂垂 Table 35: Test conditions ,119 Table 36: DC Characteristics and Operating Conditions(Asynchronous Interface 19 Table37:DC( haracteristics and Operating Conditions( Synchronous Interface)………………….120 Table38: DC Characteristics and Operating Conditions(3.3 VACCO)…………120 Table39: DC Characteristics and Operating Conditions(L。8 VVccQ)…………122 Table 40: AC Characteristics: Asynchronous Command, Address, and Data 123 Table41: AC Charactcristics: Synchronous Command, Address, and data…,…,…,…,…,…,……,125 Table42: Array Characteristics,…,… 128 PDF:CCMC05-816717818-10495 Micron Technology, Inc. reserves the right to change products or specifications without notice. Rev. 1/18 EN e 2009 Micron Technology, Inc. All rights reserved Micron Confidential and Proprietary Micron 16Gb, 32Gb, 64Gb, 128Gb Asynchronous/Synchronous NAND F eatu ures List of Figures Figure 1: Part Numbering∴…………… Figure2:;48- Pin tSoP Type 1( op view)……,…,…,,……,…,…,… 12 Figure 3: 52-Pad LGA (Top view) Figure4:l00- Ball bga(Ball-Down, Top view)………… 14 Figure5:48- Pin tsop- Type 1 CPL( Package Code:WP)∴……,…,…,…,…,…,,,,…,,,…,…,16 Figure6:52- Pad VEga.……,…,…,…,… Figure 7: 100-Ball VBGA-12mm x 18mm(Package Code: HI) ····· Figure 8: 100-Ball TBGA- 12mm x 18mm(Package Code: H2) Figure9:100- Ball lbga-12mmxl8mm( Package Code:H3)…......,,…,…,………,20 Figure 10: NAND Flash Die (LUN) Functional block diagram 21 Figure 11: Device Organization for Single- Die Package(TSOP/BGA)……,…,………………,22 Figure 12: Device Organization for Two-Die Package(TSOP) Figure 13: Device organization for Two- Die package(RGH、∴… 23 24 Figure 14: Device Organization for Four-Die Package (TSOP) 25 Figure 15: Device Organization for Four-Die Package with CE and CE2#(BGa/LGA) 4· 26 Figure 16: Device Organization for Four-Die Package with CE#f, CE2#, CE3#, and CE4#(BGA/LGA)......27 igure I: Device Organization for Eight- Die Package(BGA/LGA)…….….….………… 28 Figure 18: Array Organization per Logical Unit(①LUN)………,…,…,…,…………,… 29 Figure19: Asynchronous Command Latch Cycle,,…,,…,…,…,…,…,…,…,…,…,31 Figure 20: Asynchronous Address Latch Cycle 32 Figure21: Asynchronous Data Input Cycles………… 33 Figure22: Asynchronous Data Output Cycles…… 34 Figure 23: Asynchronous Data Output cycles (edo mode 35 Figure24:READ/BUSY# Open Drain……… …36 Figure 25: Fall and Rise(cCo=2.7-3.6V) 37 Figure26: Fall and rise(VccQ=1.7-1.95V)…………………………………37 Figure27:1 OL vS Rp(VcQ=2.7-3.6V)…………………………………………… 38 Figure28: IOL VS Rp(VccQ=1.7-1.95V)…………………… 38 Figure29: TC vS Rp………,,… 39 Figure 30: Synchronous Bus Idle/Driving Behavior 42 Figure 31: Synchronous Command Cycle 着非看 43 Figure32: Synchronous Address cycle.,,…… ·::..·.:..·· 44 igure 33: Synchronous DDR Data Input Cycles 45 Figure34: Synchronous DDR Data Output Cycles…………… 垂看着看垂D 47 Figure 35: R/B# Power-On Behavior 48 Figure 36: Activating the Synchronous Interface 51 Figure37: RESET(h) Operation……………… 54 Figure38: SYNCHRONOUS RESET(rCh) Operation……,…,…,…,…,…,…,…,…,,… 垂垂垂 Figure39: READ ID(soh) with 00h Address Operation.…,…,…,…,…,…,…,…,,…,56 Figure 40: READ ID(90h)with 20h Address Operation ∴56 Figurc41: SET FEATURES(Eh) Opcration…………,…,…,…,…,…,…,…,…,……,59 Figure 42: GET FEATURES (EEh)Operation............ 翻 59 Figure 43: READ PARAMETER (ECh)Operation 63 Figure4: READ UNIQUE ID(Dh) Operation∴………………………,73 Figure 45: READ STATUS (70h)Operation …,76 Figure 46: READ STATUS ENHANCED(78h)Operation 76 Figure 47: CHANGE READ COLUMN (05h-EOh)Operation 77 Figure48: CHANGE READ COLUMN ENHANCED(6h-EOh) Operation…,,…,… 78 Figure 49: CHANGE WRITE COLUMN (85h)Operation 79 Figure50: CHANGE ROW ADDRESS(85h) Operation………,……,81 PDF:CCMC05-816717818-10495 Micron Technology, Inc. reserves the right to change products or specifications without notice. Rev. 1/18 EN e 2009 Micron Technology, Inc. All rights reserved Micron Confidential and Proprietary Micron 16Gb, 32Gb, 64Gb, 128Gb Asynchronous/Synchronous NAND Features Figure5l: READ PAGE(o0h-30h) Operation…………,……,…,……,……,…,……,85 Figure52: READ PAGE CACHE SEQUENTIAL(31h) Operation……,…,…,,,…,86 Figure53: READ PAGE CACHE RANDOM(o0h-3lh) Operation……,…,…,,,…,……, Figure 54: READ PAGE CACHE LAST (3Fh)Operation ∴89 Figurc55: READ PAGE MULTI-PLANE(00h-32h) Opcration………,…, 91 Figure56: PROGRAM PAGE(80h-10h) Operation………,…,…,…,…,93 Figure 57: PROGRAM PAGE CACHE (80h-15h)Operation (Start) 95 Figure58: PROGRAM PAGE CACHE(BOh15h) Operation(End)………, 95 Figure 59: PROGRAM PAGE MULTI-PLANE (80h-llh)Operation 97 Figure60: ERASE BLOCK(60h-Doh) Operation…… 98 Figure 61: ERASE BLOCK MULTI-PLANE (60h-Dih)Operation ∴99 Figure 62: COPYBACK READ(00h-35h)Operation 101 Figure63: COPYBACK READ(00h-35h) with CHANGE REAd column(05h-EOh) Operation…….…….101 Figure 64: COPYBACK PROGRAM(85h-10h)Operation 102 aguri65: COPYBACK PROGRAM(85h-10h) with CHANGE WRItE column(85h) Opcration……………,102 Figure 66: COPYBACK PROGRAM MULTI-PLaNE(85h-llh)Operation 103 Figure 67: PROGRAM OTP PAGE (80h-10h)Operation...... 105 Figure68: PROGRAM OTP PAGE(80h-10 h)with CHANGE WRITE COLUMN(85h) Operation……………,106 Figure 69: PROTECT OTP AREA (80h- 10h)Operation ·...·..:· 107 Figure 70: READ OTP PAGE (00h-30h)Operation 107 Figure7l: Overshoot……… 114 Figure 72: Undershoot 114 Figure73: RESET Operation…… 129 Figure 74: READ STATUS Cycle...........................................................129 Figure75: READ STATUS ENHANCED Cycle.…,…,…,…,…,,130 Figure76: READ PARAMETER PAGE………,…,…,…,…,……,…,,……131 Figure 77: READ PAGE 13l Figurc 78: READ PAGE Opcration with CE#Dont Carc 132 Figure79: CHANGE READ COLUMN………,…,…,…,……,……,……,…,………133 Figure 80: READ PAGE CACHE SEQUENTIAL 134 Figure8l: READ PAGE CACHE RANDOM…… 音看垂 135 Figure82; READ ID Operation……,,…,…,…,…,…,…,……,,…,136 Figure 83: PROGRAM PAGE Operation 垂1 136 Figure84: PROGRAM PAGE Operation with CE#"Don' t care”……… ···:·::·.· 137 Figure 85: PROGRAM PAGE Operation with CHANGE WRITE COLUMN 137 Figure86: PROGRAM PAGE CACHE,,,…,…,…… 138 Figure 87: PROGRAM PAGE CACHE Ending on 15h 138 Figurc88: COPYBACK…… …………139 Figure89: ERASE BLOCK Operation……,,…,…,…,…,…,,…,139 Figure 90: SET FEATURES Operation l40 Figure9l: READ ID Operation………… …141 Figure 9 2: GET FEATURES Operation 142 Figure 93: RESET (FCh)Operation 143 Figure 94: READ STATUS Cycle 144 Figure 95: READ STATUS ENHANCED Operation 145 Figure96: READ PARAMETER PAGE Operation………,………,……,……,…146 Figure 97: READ PAGE Operation 147 Figurc98: CHANGE READ COLUMN……,…,……,…,…,…,…,…,…,………,………148 Figure99: READ PAGE CACHE SEQUENTIAL(1of2)……,…,…, 149 Figure 100: READ PAGE CACHE SEQUENTIAL (2 of 2) 150 Figure 101: READ PAGE CACHE RANDOM (l of2)... 151 Figure 102: READ PAGE CACHE RANDOM (2 of 2) 15l PDF:CCMC05-816717818-10495 Micron Technology, Inc. reserves the right to change products or specifications without notice. Rev. 1/18 EN e 2009 Micron Technology, Inc. All rights reserved Micron Confidential and Proprietary Micron 16Gb, 32Gb, 64Gb, 128Gb Asynchronous/Synchronous NAND Features Figure103: Multi- Plane read page(1of2)…… 4152 Figure104: Multi- Plane read Page(2of2)…………,… ∴153 Figure105: PROGRAM PAGE Operation(1of2)…,…,,…,, .154 Figure 106: PROGRAM PAGE Operation(2 of 2) 154 Figurc107: CHANGE WRITE COLUMN∴……………155 Figure108: Multi-Plane Program Page…......,…,…,…,……,,…,…,156 Figure 109: ERASE BLOCK 157 Figure110: COPYBACK(1of3)…… ···· 157 Figure 111: COPYBACK(2 of 3)................ …158 Figure 112: COPYBACK (3 of 3)...... 158 Figure 113: READ OTP PAGE.... ,159 igure114: PROGRAM OTP PAGE(1of2).................,..,160 Figure1l5: PROGRAM OTP PAGE(2of2)……….,….,….,.…,…,….,…,…,…,…,…,…,…160 Figure1l6: PROTECT OTP AREA…………………161 PDF:CCMC05-816717818-10495 Micron Technology, Inc. reserves the right to change products or specifications without notice. Rev. 1/18 EN e 2009 Micron Technology, Inc. All rights reserved Micron Confidential and Proprietary Micron 16Gb, 32Gb, 64Gb, 128Gb Asynchronous /synchron ws NAND Important Notes and Warnings Micron Technology, Inc (Micron")reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions. This document supersedes and replaces all information supplied prior to the publication hereof. You may not rely on any information set forth in this docu ment if you obtain the product described herein from any unauthorized distributor or other source not authorized by micron Automotive Applications. Products are not designed or intended for use in automotive applications unless specifi cally designated by Micron as automotive-grade by their respective data sheets. Distributor and customer/distrib utor shall assume the sole risk and liability for and shall indemnify and hold micron harmless against all claims costs,damages, and expenses and reasonable attorneys fees arising out of, directly or indirectly, any claim of product liability, personal injury, death, or property damage resulting directly or indirectly from any use of non automotive-grade products in automotive applications. Customer/ distributor shall ensure that the terms and con ditions of sale between customer/distributor and any customer of distributor/customer(1) state that micron products are not designed or intended for use in automotive applications unless specifically designated by micron as automotive-grade by their respective data sheets and(2) require such customer of distributor/customer to in demnify and hold Micron harmless against all claims, costs, damages, and expenses and reasonable attorneys fees arising out of, directly or indirectly, any claim of product liability, personal injury, death, or property damage resulting from any use of non-automotive-grade products in automotive applications Critical Applications. Products are not authorized for use in applications in which failure of the Micron compo- nent could result, directly or indirectly in death, personalinjury, or severe property or environmental damage (Critical Applications"). Customer must protect against death, personal injury, and severe property and environ mental damage by incorporating safety design measures into customer's applications to ensure that failure of the Micron component will not result in such harms Should customer or distributor purchase, use, or sell any Micron component for any critical application, customer and distributor shall indemnify and hold harmless Micron and its subsidiaries, subcontractors, and affiliates and the directors, officers, and employees ofeach against all claims, costs, damages, and expenses and reasonable attorneys fees arising out of, directly or indirectly, any claim of product liability, personal injury, or death arising in any way out of such critical application, whether or not Mi cron or its subsidiaries, subcontractors, or affiliates were negligent in the design, manufacture, or warning of the Micron product. Customer Responsibility. Customers arc responsible for thc design, manufacturc, and opcration of thcir systcms applications, and pro ducts using Micron products. ALL SEMICONDUCTOR PRODUCTS HAVE INHERENT FAIL. URE RATES AND LIMITED USEFUL LIVES. IT IS THE CUSTOMERS SOLE RESPONSIBILITY TO DETERMINE WHETHER THE MICRON PRODUCT IS SUITABLE AND FIT FOR THE CUSTOMER S SYSTEM, APPLICATION, OR PRODUCT. Customers must ensure that adequate design, manufacturing, and operating safeguards are included in customer's applications and products to eliminate the risk that personal injury, death, or severe property or er vironmental damages will result from failure of any semiconductor component Limited Warranty. In no event shall Micron be liable for any indirect, incidental, punitive, special or consequential damages (including without limitation lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges )whether or not such damages are based on tort, warranty, breach of contract or other legal theory, unless explicitly stated in a written agreement executed by micron 's du authorized representative PDF:CCMC05-816717818-10495 Micron Technology, Inc. reserves the right to change products or specifications without notice. Rev. 1/18 EN e 2009 Micron Technology, Inc. All rights reserved Micron Confidential and Proprietary Micron 16Gb, 32Gb, 64Gb, 128Gb Asynchronous(synchro pess iAND General Description Micron NAnd Flash devices include an asynchronous data interface for high-perform- ance I/O operations. These devices use a highly multiplexed 8-bit bus(DQx)to transfer commands, address, and data. There are five control signals used to implement the asynchronous data interface: CE#, CLE, ALE, WE#, and RE#. Additional signals control hardware write protection(WP#)and monitor device status(R/B#) This micron Nand Flash device additionally includes a synchronous data interface for high-pcrformancc I/O opcrations. When thc synchronous interfacc is activc, WE# be comes clk and ret becomes W/r# data transfers include a bidirectional data strobe DQS This hardware interface creates a low pin-count device with a standard pinout that re- mains the same from one density to another, enabling future upgrades to higher densi- ties with no board redesign a target is the unit of memory accessed by a chip enable signal. a target contains one or more NAND Flash die. A NAND Flash die is the minimum unit that can independently execute commands and report status. A NAND Flash die, in the ONFI specification, is referred to as a logical unit (LUN). For further details, see Device and Array Organiza- Asynchronous and Synchronous signal Descriptions Table 1: Asynchronous and Synchronous signal Definitions Asynchronous Synchronous Signal signal pe Description? ALE ALE pu Address latch enable: Loads an address from dox into the address register. CE# CE# InputChip enable: Enables or disables one or more die(LUNs)in a target CLE CLE Input Command latch enable: Loads a command from dQx into the com- and register. DQX DOX Data inputs/outputs: The bidirectional l /Os transfer address, data, and command information DQS 1/O Data strobe: Provides a synchronous reference for data input and out ut RE# W/R# Input Read enable and write/read: RE# transfers serial data from the NAND Flash to the host system when the asynchronous interface is active When the synchronous interface is active, W/R# controls the direction of DQx and dQs WE# CLK Input Write enable and clock: WE# transfers commands, addresses, and seri al data from the host system to the NANd Flash when the asynchronous interface is active. When the synchronous interface is active, CLK latches command and address cycles WP# WP# Input Write protect: Enables or disables array PROGRAM and ERASE opera- tions R/B# R/B# nal pull-up resistor. This signal indicates target array activ ss an exter- Output Ready/busy: An open-drain, active-low output that require PDF:CCMC05-816717818-10495 10 Micron Technology, Inc. reserves the right to change products or specifications without notice. Rev. 1/18 EN e 2009 Micron Technology, Inc. All rights reserved

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