CY62157ESL.PDFCY62157ESL 英文资料 CYPRESS 原厂资料，8-Mbit(

文件名称: CY62157ESL.PDF

所属分类: 硬件开发

开发工具:

文件大小: 256kb

下载次数: 0

上传时间: 2019-02-23

提供者: gxh***

下载 (256kb)

不能下载？报告错误

详细说明：CY62157ESL 英文资料 CYPRESS 原厂资料，8-Mbit(512Kx16)CYPRESS cY62157 ESL MOBL⑧ PERF。RM Pin Configuration Figure 1. 44-Pin TSOP II (Top View) A342 AAA Ao d5 444443 0□BHE 6 9口BLE 10007 8□O 10,8 37Wo14 O2囗9 O3囗10 3333 00 SS vvVWAAAAA 23456789 32口MO 10 O6囗1 30 /E 17 16 oooAgAAA 15 13 Product Portfolio Power Dissipation Vcc Range(V)[1] Speed Operating Icc, (mA) Product Range Standby, IsB2 (ns) f=1 MHz f=f (uA) max Typ/2 Max Typ (2) Max Typ [2]Max CY62157ESL Industrial 2.2 V-3.6V and 4.5 V-55V 45 1.8 3 18 2 Notes 1. Datasheet specifications are not guaranteed for Vcc in the range of 3.6V to 4.5V 2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at Vcc =3 V, and Vcc =5V, TA=25C Document #: 001-43141 ReV.*C Page 3 of 16 CYPRESS cY62157 ESL MOBL⑧ PERF。RM Maximum Ratings Output Current into Outputs(LOW) 20 mA Static Discharge Voltage Exceeding the maximum ratings may impair the useful life of the device. These user guidelines are not tested (MIL-STD-883. Method 3015) >200mA Storage Temperature 65°to+150°C atch up Current Ambient Temperature with Power Applied .55°to+125°C Operating Range Supply Voltage to Ground Potential 0.5Vto6.0V Device Range Ambient DC Voltage Applied to Outputs Temperature in High-z State[3, 4] 0.5Vto6.0V cY62157 ESL Industrial-40°ct+85°|2.2V-3.6V, DC Inout voltage/3,4] 0.5∨to6.0V and 45V-55V Electrical characteristics Over the Operating Range 45 ns Parameter Description Test Conditions Min Typ Max Unit VOH Output high voltage 2.2 Vcc-02V cC=1.5V LA N≥Vcc-0.2 V or Vin≤0.2V CC=2.0 V CDR Chip deselect to data 0 ns retention time Operation recovery time ns Figure 3. Data Retention Waveform DATA RETENTION MOD vDR≥1.5V C(min) tR or BHE. 31 Notes 10. 10Chip enable(CE)needs to be tied to CMoS levels to meet the lsB1lsB2 I ICCDR spec Other inputs can be lelt lnaing'Ond Vcc=5V,TA=25C 9. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at Vcc =3 11. Tested initially and after any design or process changes that may affect these parameters 12. Full device operation requires linear Vcc ramp from VDR to Vcc(min> 100 us or stable at Vcc(min)2 100uIs 13. BHE BLE is the AND of both BHE and BLE Deselect the chip by either disabling chip enable signals or by disabling both BHE and BLE Document #: 001-43141 ReV.*C Page 6 of 16 CYPRESS cY62157 ESL MOBL⑧ PERF。RM Switching Characteristics Over the Operating Range 45 ns Parameter[14] Description Unit Min Ma ax Read cycle tRC Read cycle time 45 ns Address to data valid 45 ns OHA Data hold from address change 10 ns ce LOW to data valid 45 ns DOE OE LOW to data valid ns OE OE LOW to LoW-7[151 5 HZOE OE HIGH to High-Zl15, 16 CE cE loW to Low -zl151 10 ns LHZCE HIGH to High-z115, 16 18 ns CE LOW to power up 0 ns D CE HIGH to power down 45 ns DBE BLE/BHE LOW to data valid 45 ns LZBE BLE/BHE LOW to Low - 15, 17] HZBE BLE/BHE HIGH to HiGH-Z[15, 16] 18 ns Write Cycle[18 Write cycle time 45 ns sce CE LOW to write end 35 ns Address setup to write end 35 ns Address hold from write end 0 ns Address setup to write start 0 ns E WE pulse width 35 ns 中ts中 BLE/BHE LOW to write end 35 ns Data setup to write end 25 ns Data hold from write end 0 tHZWE WE LOW to High-z[15, 16 18 ns LLZE WE HIGH to Low-Z115 10 Notes 14. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3 V, and output loading of the specified IoL/OH as shown in the AC Test Loads and Waveforms on page 5 15. At any temperature and voltage condition, tHZcE is less than tLZCe, tHzbE is less than tLzbe, tHZOe is less than tLzoE, and tHzwe is less than tLzwe for any device 16. tHZoE, tHzcE, tHzBE, and tHzwe transitions are measured when the outputs enter a high-impedance state 17. If both byte enables are toggled together, this value is 10 ns 18. The internal write time of the memory is defined by the overlap of WE, CE= VIl, BHE, ble or both= VL. All signals must be active to initiate a write and any of these signals can terminate a write by going inactive. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write Document #: 001-43141 ReV.*C Page 7 of 16 CYPRESS cY62157 ESL MOBL⑧ PERF。RM Switching Waveforms Figure 4. Read Cycle No. 1: Address Transition Controlled. [ 19, 201 RC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID 米Ⅹ× DATA VALID Figure 5. Read Cycle No. 2: OE Controlled [20,21] ADDRESS tRC ace HZCE OE 中HzoE DOE BHE/BLE LOE HZBE DBE HIGH HIGHMPEDANCE IMPEDANCE DATA OUT DATA VALID U 50% 50% SUPPLY CURRENT Notes 19. The device is continuously selected OE, CE= VIL, BHE, BLE, or both=VIL 20. WE is HIGH fo d cycle 21. Address valid before or similar to ce. bhe ble transition low Document #: 001-43141 ReV.*C Page 8 of 16 CYPRESS cY62157 ESL MOBL⑧ PERF。RM Switching Waveforms(continued) Figure 6. Write Cycle No 1: WE Controlled [22, 23, 24 ADDRESS CE WE BHE/BLE DATA IO E心× DATAU HZOE Figure 7. Write Cycle 2: CE Controlled (22, 23, 24 ADDRESS CE S SA HA tpWE BHE/BLE tBW OE lsi DATA DO NOTE 25 DATA N tHZE≯ Notes 22. The internal write time of the memory is defined by the overlap of WE, CE=VIL, BHE, Ble or both=VIL. All signals must be active to initiate a write and any of these signals can terminate a write by going inactive. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write 24. If ce goes HIGH simultaneously with WE=VI, the output remains in a high impedance state 25. During this period, the lOs are in output state. Do not apply input signals Document #: 001-43141 ReV.*C Page 9 of 16 CYPRESS cY62157 ESL MOBL⑧ PERF。RM Switching Waveforms(continued) Figure 8. Write Cycle 3 WE controlled, OE LOW(26, 27, 28 twc ADDRESS BHE/BLE W WE tHD tsp DATA O 交M、××人 DATAL Figure 9. Write Cycle 4: BHE/BLE Controlled, OE LOW[26,27, 281 ADDRESS CE S tscE A BHE/BLE tBW WE HZWE DATA DO NOTE 29 DATA Notes 26. The internal write time of the memory is defined by the overlap of We, ce=Vil, Bhe, ble or both VI. All signals must be active to initiate a write and any of 2> SIgnals can terminate a write by going inactive. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write. se 28. If CE goes HIGH simultaneously with WE=VH, the output remains in a high impedance state. 29. During this period, the lOs are in output state. Do not apply input signals Document #: 001-43141 ReV.*C Page 10 of 16

(系统自动生成,下载前可以参看下载内容)