您好,欢迎光临本网站![请登录][注册会员]  
文件名称: vcs user guide
  所属分类: 硬件开发
  开发工具:
  文件大小: 5mb
  下载次数: 0
  上传时间: 2019-02-23
  提 供 者: shatan******
 详细说明:VCS® MX/VCS MXi™ User Guide G-2012.09 September 2012Contents 1. Getting Started Simulator Support with Technologies 1-2 Setting Up the Simulator 14 Verifying Your System Configuration Obtaining a License 15 Setting Up Your Environment Setting Up Your C compiler 1-8 Creating a synopsys sim setup File The Concept of a Library In VCS MX 110 Library Name Mapping 1-11 Including Other Setup Files 1-12 Using SYNOPSYS SIM SETUP Environment Variable. 1-12 Displaying Setup Information 1-13 Displaying Design Information Analyzed Into a Library 1-14 Using the simulator 116 Basic Usage Model 1-17 Default time Unit and time precision ■量量 1-18 2. VCS MX FlOW Analysis 2-2 Using vhdlan 2-3 Commonly Used Analysis Options 2-3 Using vogan 2-6 Commonly Used Analysis Options 2-6 Analyzing the Design to Different Libraries 2-13 Elaboration 2-13 Using VCs 2-14 Commonly Used Options 2-15 Simulation 2-18 Interactive Mode 2-18 Batch mode 2-19 Commonly Used Runtime Options 2-19 3. Elaborating the Design Compiling or Elaborating the Design in Debug Mode Compiling or Elaborating the Design in Optimized mode 3-2 Key Elaboration Features 3-3 Initializing Verilog Memories and registers 3-3 Use mode|.,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, 3-5 Overriding Generics and Parameters 3-6 Usage Model 3-7 Checking for X and z values In Conditional Expressions 3-8 Enabling the Checking ■量 Filtering Out False Negatives 3-10 Cross Module References(XMRs 3-12 hdl xmr Procedure and hdl xmr System Task 3-13 Data Types Supported 3-13 VHDL Referencing Verilog using hdl xmr procedure 3-14 Verilog Referencing VHDL objects using $hdl xmr 3-16 Usage model 3-17 Hdl xmr Support for VHDL Variables 3-18 Datatype Support and Usage Examples 3-19 VCS MX V2K Configurations and libmaps 3-24 Library Mapping Files 3-25 Configurations 3-26 Usage Model 3-30 Example 3-30 Using -liblist Option 3-35 Evaluating the Active Events When Limiting the Exposure of Race Conditions,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, 3-38 Lint Warning Message for Missing endcelldefine 3-39 Error/Warning Message Control ........... 3-43 Controlling Error Messages 3-45 Controlling Warning Messages 3-45 Controlling Lint Messages ■■量 3-47 Suppressing Lint, Warning, and Error Messages....... 3-48 Error Conditions and messages That cannot be disabled 3-48 Using Message Control Options Together 3-49 Message Control Examples 3-49 Obsolete Compile-Time Options for Controlling Messages 3-59 4. Simulating the Design Using dVE 4-2 Using UCLI :····::·:··1·:····· 4-3 ucli2Proc command 4-5 Options for Debugging Using DVE and UCLI 4-6 Key Runtime Features 4-8 Overriding Generics at Runtime 4-8 Usage Model Passing Values from the Runtime Command Line 4-12 VCS MX Supports simv -f 4-14 Limitations 4-14 Specifying a Long Time Before Stopping The Simulation.. 4-15 5. Diagnostics Using Diagnostics 5-2 Using Option 5-2 Using Smartlog 5-4 Compile-time Diagnostics...............5-5 Libconfig Diagnostics 5-5 Example 5-5 Timescale Diagnostics 5-8 EXample 5-8 Runtime Diagnostics 5-12 Diagnostics for VPI/HPI PLI Applications 5-12 Keeping the UCLI/DVE Prompt Active After a Runtime Error 5-15 UCLI USe Model 5-15 DVE USe Model 5-17 UCLI Usage Example 5-19 Limitations 5-21 Diagnosing Quickthread Issues in SystemC 5-21 Quickthread Overruns Its Allocated Stack 5-22 Simulation Runs Out of Memory Due to Quickthread Stacks 5-23 Reducing or Turning Off Redzones 5-24 Post-processing Diagnostics 5-25 Using the vpdutil Utility to Generate Statistics 5-25 The vpdutil Utility Syntax............. 5-25 Options 5-26 6. VCS Multicore Technology Application Level Parallelism VCS Multicore Technology Options 6-30 Use Model for assertion simulation 6-32 Use model for toggle and functional coverage. ..... 6-32 Use Model for VPD dumping 6-32 Running VCS Multicore Simulation 日画 量日量 6-33 Assertion simulation 6-33 oggle Coverage 6-34 Functional Coverage 6-35 VPD FIle 6-37 Parallel salF 6-38 Customary SAIF System Function Entries........ 6-38 Enabling Parallel SalF 6-39 Limitations 6-39 7. VP, Vcd, and evcd utilities Advantages of VPd 7-2 Dumping a VPD File ■日日 Using system Tasks 7-3 Enable and Disable dumping 7-4 Override the vpd filename 7-7 Dump Multi-dimensional Arrays and Memories 7-8 Using $vcdplusmemorydump 7-17 Capture Delta Cycle Information 7-18 Dumping an EVCD File 7 Limitations 7-21 Post-processing Utilities 7-23 The vcdiff Utility 7-24 The vcdiff Utility syntax 7-25 The vcat Utility 7-32 The vcat Utility Syntax 7-32 Generating Source Files from Vcd Files 7-36 Writing the Configuration File 7-38 The vcsplit Utility 7-42 The vcsplit Utility Syntax 7-42 The vcd vpd Utility 7-46 Options for specifying EVCD options 7-47 The vpd2vcd Utility 7-48 The Command file Syntax 7-54 The vpdmerge Utility 7-57 The vpdutil Utility 7-61 8. Performance Tuning Compile-time Performance 8-3 Incremental compilation 8-3 Compile Once and Run Many Times 8-4 Parallel Compilation 8-4 Runtime performance 8-5 Using Radiant Technology 8-5 Compiling With Radiant Technology 8-6 Applying Radiant Technology to Parts of the Design.. 8-6 Improving Performance When Using PLls 8-15 Usage Model 8-16 Impact on Performance 8-19 Obtaining VCS Consumption of CPU Resources 8-20 Use model 8-20 Compile time 8-20 Simulation Time 8-21 9. Gate-evel simulation SDF Annotation 9-2 Using Unified SDF Feature 9-2 Using $sdf annotate System Task 9-3 Using-xIrm Option for SDF Retain, Gate Pulse Propagation, and Gate Pulse Detection Warning 9-5 Using Optimistic Mode in SDF 96 Using Gate Pulse Propagation 9-7 Generating Warnings During Gate Pulses 9-8 X Precompiling an SDF File 量日 Creating the precompiled version of the sdf file.... 9-9 SDF Configuration File 9-10 Delay objects and Constructs........... 9-11 SDF Configuration File commands 9-12 approx command 9-12 mtm command 9-13 scale command 9-14 SDF EXample with Configuration File 9-15 Delays and Timing 9-17 Transport and Inertial Delays 9-18 Different Inertial Delay Implementations..,..... 9-20 Enabling Transport Delays 9-22 Pulse control 9-23 Pulse Control with Transport Delays 9-25 Pulse Control with Inertial Delays 9-27 Specifying Pulse on Event or Detect Behavior..... 9-32 Specifying the Delay Mode 9-36 Using the Configuration File to Disable Timing 9-38 Using the timopt Timing Optimizer 量■ 38 Editing the timopt. cfg File 9-41 Editing Potential Sequential Device Entries 9-41 Editing Clock Signal Entries 9-42 Using scan Simulation Optimizer 9-43 ScanOpt Config File Format 9-44 ScanOpt Assumptions 9-45
(系统自动生成,下载前可以参看下载内容)

下载文件列表

相关说明

  • 本站资源为会员上传分享交流与学习,如有侵犯您的权益,请联系我们删除.
  • 本站是交换下载平台,提供交流渠道,下载内容来自于网络,除下载问题外,其它问题请自行百度
  • 本站已设置防盗链,请勿用迅雷、QQ旋风等多线程下载软件下载资源,下载后用WinRAR最新版进行解压.
  • 如果您发现内容无法下载,请稍后再次尝试;或者到消费记录里找到下载记录反馈给我们.
  • 下载后发现下载的内容跟说明不相乎,请到消费记录里找到下载记录反馈给我们,经确认后退回积分.
  • 如下载前有疑问,可以通过点击"提供者"的名字,查看对方的联系方式,联系对方咨询.
 相关搜索: vcsuserguide
 输入关键字,在本站1000多万海量源码库中尽情搜索: